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參數(shù)資料
| 型號： | MC10135P |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 10K SERIES, POSITIVE EDGE TRIGGERED JBAR-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 108K |
| 代理商： | MC10135P |
MC10135
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30
°C
+25
°C
+85
°C
Characteristic
Symbol
Under
Test
Min
Max
Min
Typ
Max
Min
Max
Unit
Power Supply Drain Current
IE
8
75
54
68
75
mAdc
Input Current
IinH
6,7,9,10,11
4,5,12,13
425
620
265
390
265
390
Adc
IinL
4,5,6,7,9,
10,11,12,13
0.5
0.3
Adc
Output Voltage
Logic 1
VOH
2
2 (3.)
–1.060
–0.890
–0.960
–0.810
–0.890
–0.700
Vdc
Output Voltage
Logic 0
VOL
3
3 (3.)
–1.890
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
2 (4.)
–1.080
–0.980
–0.910
Vdc
Threshold Voltage
Logic 0
VOLA
3
3 (4.)
–1.655
–1.630
–1.595
Vdc
Switching Times (50
Load)
Clock Input
ns
Propagation Delay
t9+2+
t9+2–
2
1.8
5.0
1.8
3.0
4.5
1.8
4.6
Rise Time
(20 to 80%)
t2+, t3+
2, 3
1.1
4.8
1.1
2.0
4.5
1.1
4.7
Fall Time
(20 to 80%)
t2–, t3–
2, 3
1.1
4.8
1.1
2.0
4.5
1.1
4.7
Set Input
ns
Propagation Delay
t5+2+
t12+15+
t5+3–
t12+14–
2
15
3
14
1.8
5.6
1.8
3.0
5.0
1.8
5.2
Reset Input
ns
Propagation Delay
t4+2–
t4+3–
t13+15–
t13+14+
2
3
15
14
1.8
5.6
1.8
3.0
5.0
1.8
5.2
Setup Time
tsetup
7
2.5
1.0
2.5
ns
Hold Time
thold
7
1.5
1.0
2.5
ns
Toggle Frequency (Max)
ftog
2
125
140
125
MHz
1. Individually test each input; apply VIHmax to pin under test.
2. Individually test each input; apply VILmin to pin under test.
3. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHmax
VILmin
4. Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHAmax
VILAmin
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