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參數(shù)資料
| 型號： | MC10131L |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 10K SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 109K |
| 代理商： | MC10131L |
MC10131
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30
°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25
°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85
°C
–0.700
–1.825
–1.035
–1.440
–5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V
)
Characteristic
Symbol
Under
Test
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
Power Supply Drain Current
IE
8
1, 16
Input Current
IinH
4
5
6
7
9
4
5
6
7
9
8
1, 16
IinL
4, 5*
6, 7, 9*
*
8
1, 16
Output Voltage
Logic 1
VOH
2
[
5
7
8
1, 16
Output Voltage
Logic 0
VOL
2
3
[
5
7
8
1, 16
Threshold Voltage
Logic 1
VOHA
2
[
5
7
9
8
1, 16
Threshold Voltage
Logic 0
VOLA
2
3
[
5
7
9
8
1, 16
Switching Times
(50
Load)
Clock Input
+1.11Vdc
Pulse In
Pulse Out
–3.2 V
+2.0 V
Propagation Delay
t9+2–
t9+2+
t6+2+
t6+2–
2
7
9
6
2
8
1, 16
Rise Time
(20 to 80%)
t2+
2
7
9
2
8
1, 16
Fall Time
(20 to 80%)
t2–
2
9
2
8
1, 16
Set Input
Propagation Delay
t5+2+
t12+15+
t5+3–
t12+14–
2
15
3
14
6
9
5
12
5
12
2
15
3
14
8
1, 16
Reset Input
Propagation Delay
t4+2–
t13+15–
t4+3–
t13+14+
2
15
3
14
6
9
4
13
4
13
2
15
3
14
8
1, 16
Setup Time
tsetup
7
6, 7
2
8
1, 16
Hold Time
thold
7
6, 7
2
8
1, 16
Toggle Frequency (Max)
ftog
2
6
2
8
1, 16
* Individually test each input applying VIH or VIL to input under test.
[ Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHmax
VILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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