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參數(shù)資料
| 型號(hào)： | MC10131L |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 鎖存器 |
| 英文描述： | 10K SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 109K |
| 代理商： | MC10131L |
MC10131
http://onsemi.com
2
ELECTRICAL CHARACTERISTICS
Test Limits
Pin
Under
–30
°C
+25
°C
+85
°C
Characteristic
Symbol
Under
Test
Min
Max
Min
Typ
Max
Min
Max
Unit
Power Supply Drain Current
IE
8
62
45
56
62
mAdc
Input Current
IinH
4
5
6
7
9
525
350
390
425
330
220
245
265
330
220
245
265
Adc
IinL
4, 5*
6, 7, 9*
0.5
0.3
Adc
Output Voltage
Logic 1
VOH
2
[
–1.060
–0.890
–0.960
–0.810
–0.890
–0.700
Vdc
Output Voltage
Logic 0
VOL
2
3
[
–1.890
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Threshold Voltage
Logic 1
VOHA
2
[
–1.080
–0.980
–0.910
Vdc
Threshold Voltage
Logic 0
VOLA
2
3
[
–1.655
–1.630
–1.595
Vdc
Switching Times (50
Load)
Clock Input
ns
Propagation Delay
t9+2–
t9+2+
t6+2+
t6+2–
2
1.7
4.6
1.8
3.0
4.5
1.8
5.0
Rise Time
(20 to 80%)
t2+
2
1.0
4.6
1.1
2.5
4.5
1.1
4.9
Fall Time
(20 to 80%)
t2–
2
1.0
4.6
1.1
2.5
4.5
1.1
4.9
Set Input
ns
Propagation Delay
t5+2+
t12+15+
t5+3–
t12+14–
2
15
3
14
1.7
4.4
1.8
2.8
4.3
1.8
4.8
Reset Input
ns
Propagation Delay
t4+2–
t13+15–
t4+3–
t13+14+
2
15
3
14
1.7
4.4
1.8
2.8
4.3
1.8
4.8
Setup Time
tsetup
7
2.5
ns
Hold Time
thold
7
1.5
ns
Toggle Frequency (Max)
ftog
2
125
160
125
MHz
* Individually test each input applying VIH or VIL to input under test.
[ Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHmax
VILmin
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