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參數(shù)資料
| 型號(hào)： | MC100LVEL38DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Replaced by TPS2051B : 0.7A, 2.7-5.5V Single Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC 0 to 85 |
| 中文描述： | 100LVEL SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 5 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 128K |
| 代理商： | MC100LVEL38DW |
SEMICONDUCTOR TECHNICAL DATA
4–1
REV 1
Motorola, Inc. 1996
10/94
÷
÷
The MC100LVEL38 is a low skew
÷
2,
÷
4/6 clock generation chip
designed explicitly for low skew clock generation applications. The
MC100EL38 is pin and functionally equivalent to the MC100LVEL38 but
is specified for operation at the standard 100K ECL voltage supply. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended LVECL or, if positive power supplies are
used, LVPECL input signal. In addition, by using the VBB output, a
sinusoidal source can be AC coupled into the device (see Interfacing
section of the ECLinPS
Data Book DL140/D). If a single-ended input is
to be used, the VBB output should be connected to the CLK input and
bypassed to ground via a 0.01
μ
F capacitor. The VBB output is designed to
act as the switching reference for the input of the LVEL38 under
single-ended input conditions, as a result, this pin can only source/sink up
to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The Phase_Out output will go HIGH for one clock cycle whenever the
÷
2 and the
÷
4/6 outputs are both transitioning from a LOW to a HIGH.
This output allows for clock synchronization within the system.
Upon startup, the internal flip-flops will attain a random state; therefore,
for systems which utilize multiple LVEL38s, the master reset (MR) input
must be asserted to ensure synchronization. For systems which only use
one LVEL38, the MR pin need not be exercised as the internal divider
design ensures synchronization between the
÷
2 and the
÷
4/6 outputs of a
single device.
50ps Output-to-Output Skew
Synchronous Enable/Disable
Master Reset for Synchronization
75k
Internal Input Pulldown Resistors
>1500V ESD Protection
Low Voltage VEE Range of –3.0 to –3.8V
CLK
Pinout: 20-Lead SOIC
(Top View)
CLK
MR
VCC
17
18
16
15
14
13
12
4
3
5
6
7
8
9
Q0
11
10
Q1
Q1
Q2
Q2
Q3
Q3
VEE
EN
19
20
2
1
VCC
Q0
P
P
DIV_SEL
VBB
VCC
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
1
20
PIN
FUNCTION
CLK
EN
MR
VBB
Q0, Q1
Q2, Q3
DIVSEL
Phase_Out
Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff
÷
2 Outputs
Diff
÷
4/6 Outputs
Frequency Select Input
Phase Sync Signal
PIN DESCRIPTION
CLK
Z
ZZ
X
EN
L
H
X
MR
L
L
H
FUNCTION
Divide
Hold Q0–3
Reset Q0–3
FUNCTION TABLE
Z = Low-to-High Transition
ZZ = High-to-Low Transition
DIVSEL
Q2, Q3 OUTPUTS
0
1
Divide by 4
Divide by 6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100EL38DW | ±2, ±4/6 Clock Generation Chip |
| MC100LVEL40DW | Single, Current-Limited, Power-Distribution Switch 5-SOT-23 -40 to 85 |
| MC100LVEL51D | Single, Current-Limited, Power-Distribution Switch 8-SOIC -40 to 85 |
| MC100LVEL56DW | Single, Current-Limited, Power-Distribution Switch 8-MSOP-PowerPAD -40 to 85 |
| MC100EL56DW | Dual Differential 2:1 Multiplexer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100LVEL38DWG | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL38DWR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL38DWR2G | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL39DW | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MC100LVEL39DWG | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V ECL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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