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參數(shù)資料
| 型號(hào)： | MC100EP35MNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLIP FLOP JK 3.3/5V ECL 8-DFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | 100EP |
| 功能： | 復(fù)位 |
| 類型： | JK 型 |
| 輸出類型： | 差分 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 1 |
| 頻率 - 時(shí)鐘： | 3GHz |
| 延遲時(shí)間 - 傳輸： | 410ps |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-VFDFN 裸露焊盤 |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC100EP35MNR4GOSCT |
MC10EP35, MC100EP35
http://onsemi.com
6
Table 11. AC CHARACTERISTICS VCC = 0 V; VEE = 3.0 V to 5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 15)
40°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fmax
Maximum Frequency
> 3
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
R, CLK to Q, Q
200
400
480
200
410
490
200
420
575
ps
tRR
Reset Recovery
150
80
150
90
150
100
ps
tS
tH
Setup Time
Hold Time
150
50
150
50
150
80
ps
tPW
Minimum Pulse width
RESET
550
400
550
400
550
400
ps
tJITTER
CycletoCycle Jitter
0.2
< 1
0.2
< 1
0.2
< 1
ps
tr
tf
Output Rise/Fall Times
Q, Q
(20% 80%)
70
120
170
80
130
180
100
150
200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
15.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
0
100
200
300
400
500
600
700
800
900
0
1000
2000
3000
4000
5000
Figure 2. Fmax/Jitter
FREQUENCY (MHz)
1
2
3
4
5
6
7
8
9
(JITTER)
V
OUTpp
(mV)
JITTER
OUT
ps
(RMS)
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