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參數(shù)資料
| 型號： | MC100EP196FAG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | 100EP |
| 標(biāo)片/步級數(shù)： | 1024 |
| 功能： | 可編程 |
| 延遲到第一抽頭： | 2.36ns |
| 接頭增量： | 10ps |
| 可用的總延遲： | 2.36ns ~ 12.258ns |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-LQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | MC100EP196FAGOS |
MC100EP196
http://onsemi.com
13
Cascading Multiple EP196s
To increase the programmable range of the EP196,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP196s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E196.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range; however, this
increase is at the expense of a longer minimum delay.
Figure 6 illustrates the interconnect scheme for cascading
two EP196s. As can be seen, this scheme can easily be
expanded for larger EP196 chains. The D10 input of the
EP196 is the cascade control pin and when assert
HIGH switches output pin CASCADE to HIGH and
pin CASCADE to LOW. With the interconnect scheme of
Figure 6 when D10 is asserted, it signals the need for a larger
programmable range than is achievable with a single device.
The A11 address can be added to generate a cascade output
for the next EP196. For a 2device configuration, A11 is not
required.
Figure 6. Cascading Interconnect Architecture
VEE
D0
VCC
Q
FTUNE
VCC
CASCADE
EN
SETMAX
V
CC
V
EE
LEN
D2 D1
CASCADE
SETMIN
VBB
IN
VEE
D8
VEF
D3
D4
D5
D6
D7
D9
D10
IN
VCF
INPUT
OUTPUT
EP196
CHIP #2
EP196
CHIP #1
ADDRESS BUS
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Need if Chip #3 is used
DAC
VEE
D0
VCC
Q
FTUNE
VCC
CASCADE
EN
SETMAX
V
CC
V
EE
LEN
D2 D1
CASCADE
SETMIN
VBB
IN
VEE
D8
VEF
D3
D4
D5
D6
D7
D9
D10
IN
VCF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100EP196FAG | 制造商:ON Semiconductor 功能描述:Delay Line IC |
| MC100EP196FAR2 | 功能描述:延遲線/計時元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP196FAR2G | 功能描述:延遲線/計時元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| MC100EP210S | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V1:5 Dual Differential LVDS Compatible Clock Driver |
| MC100EP210S_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V 1:5 Dual Differential LVDS Compatible Clock Driver |
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