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參數(shù)資料
| 型號(hào)： | MC100EP111FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大?。?/td> | 116K |
| 代理商： | MC100EP111FA |
7
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC100EP111/D
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
624
Low-Voltage 1:10 Differential
ECL/PECL/HSTL Clock Driver
The MC100EP111 is a low skew 1–to–10 differential driver, designed
with clock distribution in mind. It accepts two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single–ended if the VBB output is used. HSTL inputs can be used when
the EP111 is operating under PECL conditions. The selected signal is
fanned out to 10 identical differential outputs.
100ps Part–to–Part Skew typical
35ps Output–to–Output Skew typical
Differential Design
VBB Output
Low Voltage VEE Range of –2.25 to –3.8V for ECL
Low Voltage VCC Range of +2.25 to +3.8V for PECL and HSTL
75k Input Pulldown Resistors
ECL/PECL Outputs
The EP111 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize
gate–to–gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.
To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into
50
, even if only one side is being used. In most applications, all ten differential pairs will be used and therefore terminated. In
the case where fewer than ten pairs are used, it is necessary to terminate at least the output pairs on the same package side as
the pair(s) being used on that side, in order to maintain minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 10–20ps) of the output(s) being used which, while not being catastrophic to most designs, will
mean a loss of skew margin.
The MC100EP111, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows
the EP111 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the
EP111’s performance to distribute low skew clocks across the backplane or the board. In a PECL environment, series or
Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL,
designers should refer to Motorola Application Note AN1406/D.
The MC100EP111 may be driven single–endedly utilizing the VBB bias output with the CLK0 input. If a single–ended signal
is to be used, the VBB pin should be connected to the CLK0 input and bypassed to ground via a 0.01 F capacitor. The VBB
output can only source/sink 0.2mA; therefore, it should be used as a switching reference for the MC100EP111 only. Part–to–Part
Skew specifications are not guaranteed when driving the MC100EP111 single–endedly.
Rev 1
MC100EP111
LOW–VOLTAGE
1:10 DIFFERENTIAL
ECL/PECL/HSTL
CLOCK DRIVER
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
See Upgrade Product – MC100ES6111
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| MC100EP116 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3 V / 5 V Hex Differential Line Receiver/Driver |
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