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參數(shù)資料
| 型號： | MC-4R96CPE6C-745 |
| 廠商： | NEC Corp. |
| 英文描述： | Direct Rambus DRAM RIMM Module 96M-BYTE 48M-WORD x 16-BIT |
| 中文描述： | 直接Rambus的內存模塊9600 RIMM的技嘉4800字× 16位 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 131K |
| 代理商： | MC-4R96CPE6C-745 |
Preliminary Data Sheet M14806EJ2V0DS00
9
MC-4R96CPE6C
AC Electrical Specifications
Symbol
Parameter and Conditions
MIN.
TYP.
MAX.
Unit
Z
Module Impedance
25.2
28
30.8
T
PD
Average clock delay from finger to finger of all RSL clock nets
-845
1.40
ns
(CTM, CTMN,CFM, and CFMN)
-745
1.40
-653
1.40
T
PD
Propagation delay variation of RSL signals with respect to TPD
Note1,2
21
+21
ps
T
PD-CMOS
Propagation delay variation of SCK and CMD signals with respect to
an average clock delay
Note1
100
+100
ps
V
α
/V
IN
Attenuation Limit
-845
14
%
-745
14
-653
9
V
XF
/V
IN
Forward crosstalk coefficient
-845
3
%
(300ps input rise time 20% - 80%)
-745
3
-653
3
V
XB
/V
IN
Backward crosstalk coefficient
-845
1.8
%
(300ps input rise time 20% - 80%)
-745
1.8
-653
1.8
R
DC
DC Resistance Limit
-845
0.7
-745
0.7
-653
0.7
Notes 1.
T
PD
or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM,
CTMN, CFM, and CFMN).
2.
If the RIMM module meets the following specification, then it is compliant to the specification.
If the RIMM module does not meet these specifications, then the specification can be adjusted by the
“Adjusted
T
PD
Specification” table.
Adjusted
T
PD
Specification
Symbol
Parameter and conditions
Adjusted MIN./MAX.
Absolute
Unit
MIN.
MAX.
T
PD
Propagation delay variation of RSL signals with respect to T
PD
+/
[17+(18*N*
Z0)]
Note
30
+30
ps
Note
N = Number of RDRAM devices installed on the RIMM module.
Z0 = delta Z0% = (MAX. Z0
MIN. Z0) / (MIN. Z0)
(MAX. Z0 and MIN. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers
on the module.)
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