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參數(shù)資料
| 型號(hào)： | MC-454CB64S |
| 廠商： | NEC Corp. |
| 英文描述： | 4M-Word By 64-BIT Dynamic RAM Module(動(dòng)態(tài)RAM模塊) |
| 中文描述： | 分詞，64位動(dòng)態(tài)RAM模塊（動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 138K |
| 代理商： | MC-454CB64S |
6
MC-454CB64S
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
Burst length
=
1, t
RC
≥
t
RC(MIN.)
/CAS latency = 2
-A80
360
mA
1
-A10
360
-A10B
280
/CAS latency = 3
-A80
460
-A10
460
-A10B
360
Precharge standby current in
I
CC2
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
4
mA
power down mode
I
CC2
PS
CKE
≤
V
IL(MAX.)
, t
CK
=
∞
2
Precharge standby current in
non power down mode
I
CC2
N
CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
Input signals are changed one time during 30
ns.
80
mA
I
CC2
NS
CKE
≥
V
IH(MIN.)
, t
CK
=
∞
, Input signals are stable.
24
Active standby current in
I
CC3
P
CKE
≤
V
IL(MAX.)
, t
CK
=
15
ns
20
mA
power down mode
I
CC3
PS
CKE
≤
V
IL(MAX.)
, t
CK
=
∞
16
Active standby current in
non power down mode
I
CC3
N
CKE
≥
V
IH(MIN.)
, t
CK
=
15
ns, /CS
≥
V
IH(MIN.)
,
Input signals are changed one time during 30
ns.
100
mA
I
CC3
NS
CKE
≥
V
IH(MIN.)
, t
CK
=
∞
, Input signals are stable.
40
Operating current
I
CC4
t
CK
≥
t
CK(MIN.)
, I
O
= 0
mA
/CAS latency = 2
-A80
660
mA
2
(Burst mode)
-A10
520
-A10B
440
/CAS latency = 3
-A80
780
-A10
660
-A10B
660
Refresh current
I
CC5
t
RC
≥
t
RC(MIN.)
/CAS latency = 2
-A80
520
mA
3
-A10
520
-A10B
420
/CAS latency = 3
-A80
540
-A10
540
-A10B
460
Self refresh current
I
CC6
CKE
≤
0.2
V
-**
4
mA
-**L
2
Input leakage current
I
I(L)
V
I
=
0 to 3.6
V,
All other pins not under test =
0 V
–
4
+4
μ
A
Output leakage current
I
O(L)
D
OUT
is disabled, V
O
=
0 to 3.6
V
–1.5
+1.5
μ
A
High level output voltage
V
OH
I
O
=
–
2.0
mA
2.4
V
Low level output voltage
V
OL
I
O
=
+
2.0
mA
0.4
V
Notes 1.
I
CC1
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC1
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
2
. I
CC4
depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, I
CC4
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
3.
I
CC5
is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
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