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參數(shù)資料
| 型號： | MC-4516DC72 |
| 廠商： | NEC Corp. |
| 英文描述： | 16 M-Word By 72-Bit Synchronous Dynamic RAM Module(同步動態(tài)RAM 模塊) |
| 中文描述： | 16米，由72個字位同步動態(tài)隨機存儲器模塊（同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 211K |
| 代理商： | MC-4516DC72 |
9
MC-4516DC72
Synchronous Characteristics
[ MC-4516DC72-A10, 4516DC72-A12 ]
Parameter
Symbol
-A10
-A12
Unit
Note
MIN.
MAX.
MIN.
MAX.
Clock cycle time
/CAS latency = 3
t
CK3
10
(100 MHz)
12
(83
MHz)
ns
/CAS latency = 2
t
CK2
15
(67 MHz)
18
(55
MHz)
ns
Access time from CLK
/CAS latency = 3
t
AC3
8.5
9.5
ns
1
/CAS latency = 2
t
AC2
9.5
11.5
ns
1
Input CLK duty cycle
40
60
40
60
%
Data-out hold time
t
OH
2.5
2.5
ns
1
Data-out low-impedance time
t
LZ
0
0
ns
Data-out high-impedance time
t
HZ
3.5
8.0
3.5
8.0
ns
Data-in setup time
t
DS
3.0
3.5
ns
Data-in hold time
t
DH
1.5
2.0
ns
Address setup time
t
AS
3.5
3.5
ns
Address hold time
t
AH
0.5
0.5
ns
CKE setup time
t
CKS
3.5
3.5
ns
CKE hold time
t
CKH
0.5
0.5
ns
CKE setup time (Power down
exit)
Command (/CS0, /CS1, /RAS, /CAS, /WE, DQM)
setup time
Command (/CS0, /CS1, /RAS, /CAS, /WE, DQM)
hold time
t
CKSP
3.0
3.5
ns
t
CMS
3.5
3.5
ns
t
CMH
0.5
0.5
ns
Note 1.
Output load
Output
Z = 50
1.4 V
50 pF
50
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