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參數(shù)資料
| 型號(hào)： | MC-42S8LFG64S |
| 廠商： | NEC Corp. |
| 英文描述： | 8 M-Word By 64-Bit Synchronous Dynamic RAM Module(同步動(dòng)態(tài)RAM 模塊) |
| 中文描述： | 八米，由64個(gè)字位同步動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊（同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 267K |
| 代理商： | MC-42S8LFG64S |
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5
MC-42S8LFG64S
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
MIN.
MAX.
Unit
Notes
Operating current
I
CC1
/RAS, /CAS cycling
t
RAC
= 50 ns
648
mA
1, 2, 3
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 60 ns
568
Standby current
I
CC2
/RAS, /CAS
≥
V
IH (MIN.)
, I
O
= 0 mA
8.0
mA
/RAS, /CAS
≥
V
CC
0.2 V, I
O
= 0 mA
1.6
/RAS only refresh current
I
CC3
/RAS cycling, /CAS
≥
V
IH (MIN.)
t
RAC
= 50 ns
648
mA
1, 2, 3 ,4
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 60 ns
568
Operating current
I
CC4
/RAS
≤
V
IL (MAX.)
, /CAS cycling
t
RAC
= 50 ns
528
mA
1, 2, 5
(Hyper page mode (EDO))
t
HPC
= t
HPC (MIN.)
, I
O
= 0 mA
t
RAC
= 60 ns
448
/CAS before /RAS
I
CC5
/RAS cycling
t
RAC
= 50 ns
648
mA
1, 2
refresh current
t
RC
= t
RC (MIN.)
, I
O
= 0 mA
t
RAC
= 60 ns
568
/CAS before /RAS
I
CC6
/CAS before /RAS refresh :
t
RAS
≤
300 ns
4.0
mA
1, 2
long refresh current
t
RC
= 31.3
μ
s
(4,096 cycles / 128 ms)
/RAS, /CAS :
V
CC
0.2 V
≤
V
IH
≤
V
IH (MAX.)
0 V
≤
V
IL
≤
0.2 V
Standby :
t
RAS
≤
1
μ
s
4.8
mA
1, 2
/RAS, /CAS
≥
V
CC
0.2 V
Address : V
IH
or V
IL
/WE, /OE : V
IH
I
O
= 0 mA
/CAS before /RAS
I
CC7
/RAS, /CAS :
3.2
mA
2
self refresh current
t
RASS
= 5 ms
V
CC
0.2 V
≤
V
IH
≤
V
IH (MAX.)
0 V
≤
V
IL
≤
0.2 V
I
O
= 0 mA
Input leakage current
I
I (L)
V
I
= 0 to 3.6 V
40
+40
μ
A
All other pins not under test = 0 V
Output leakage current
I
O (L)
V
O
= 0 to 3.6 V
5
+5
μ
A
Output is disabled (Hi
Z)
High level output voltage
V
OH
I
O
=
2.0 mA
2.4
V
Low level output voltage
V
OL
I
O
= +2.0 mA
0.4
V
Notes 1.
I
CC1
, I
CC3
, I
CC4
, I
CC5
and I
CC6
depend on cycle rates (t
RC
and t
HPC
).
2.
Specified values are obtained with outputs unloaded.
3.
I
CC1
and I
CC3
are measured assuming that address can be changed once or less during /RAS
≤
V
IL (MAX.)
and
/CAS
≥
V
IH (MIN.)
.
4.
I
CC3
is measured assuming that all column address inputs are held at either high or low.
5.
I
CC4
is measured assuming that all column address inputs are switched only once during each hyper page
(EDO) cycle.
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