參數(shù)資料
型號(hào)： MBM29DL32TF70TN
廠商： FUJITSU LTD
元件分類： PROM
英文描述： 2M X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝： PLASTIC, TSOP1-48
文件頁數(shù)： 25/70頁
文件大小： 862K
代理商： MBM29DL32TF70TN
MBM29DL32TF/BF-70
31
write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is
latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever
happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence,
the system is not required to provide further controls or timings. The device will automatically provide adequate
internally generated program pulses and verify the programmed cell margin.
The system can determine the status of the program operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) ,
or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location which is being programmed.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags Table”.) Therefore, the devices require that a valid address to the devices be supplied by the
system at this particular instance. Hence, Data Polling must be performed at the memory location which is being
programmed.
If hardware reset occurs during the programming operation, it is impossible to guarantee the data being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“1. Embedded ProgramTM Algorithm” in sFLOW CHART illustrates the Embedded ProgramTM Algorithm using
typical command strings and bus operations.
4.
Program Suspend/Resume
The Program Suspend command allows the system to interrupt a program operation so that data can be read
from any address. Writing the Program Suspend command (B0h) during the embedded Program operation
immediately suspends the programming. The Program Suspend command may also be issued during a pro-
gramming operation while an erase is suspended. The bank addresses of sector being programmed should be
set when writing the Program Suspend command.
When the Program Suspend command is written during a programming process, the device halts the program
operation within 1
s and updates the status bits.
After the program operation has been suspended, the system can read data from any address. The data at
program-suspended address is not valid. Normal read timing and command definitions apply.
After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses
of sectors being suspended should be set when writing the Program Resume command. The system can
determine the program operation status using the DQ7 or DQ6 status bits, just as in the standard program
operation. See “Write Operation Status” for more information.
The system also writes Autoselect command sequence in the Program Suspend mode. The device allows reading
autoselect codes at the addresses within programming sectors, since the codes are not stored in the mamory.
When the device exits from the Autoselect mode, the device reverts to the Program Suspend mode, and is ready
for another valid operation. See “Autoselect Command Sequence” for more information.
The system must write the Program Resume command (address bits are “Bank Address”) to exit from the
Program Suspend mode and continue programming operation. Further writes of the Resume command are
ignored. Another Program Suspend command can be written after the device resumes programming.
5.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any
controls or timings during these operations.
The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or
RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command
sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the
device returns to read the mode.
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