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參數(shù)資料
| 型號： | MBM29DL32TF70TN |
| 廠商： | FUJITSU LTD |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 70 ns, PDSO48 |
| 封裝： | PLASTIC, TSOP1-48 |
| 文件頁數(shù)： | 20/70頁 |
| 文件大?。?/td> | 862K |
| 代理商： | MBM29DL32TF70TN |
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MBM29DL32TF/BF-70
27
command sequence is illustrated in “MBM29DL32TF/BF Command Definitions Table” (sDEVICE BUS OPER-
ATION). (Refer to “2. Autoselect Command” in sCOMMAND DIFINITIONS.)
In WORD mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu
= 04h) . A read cycle
at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended
Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes
at addresses of 0Eh and 0Fh. Notice that the above applies to WORD mode; the addresses and codes differ
from those of BYTE mode. (Refer to “MBM29DL32TF/BF Sector Group Protection Verify Autoselect Codes
Tables” and “MBM29DL32TF/BF Extended Autoselect Code Tables” in sDEVICE BUS OPERATION.)
In the case of applying VID on A9, since both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation
cannot be executed.
5.
Read Mode
The MBM29DL32TF/BF have two control functions required to obtain data at the outputs. CE is the power control
and used for a device selection. OE is the output control and used to gate data to the output pins if a device is
selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time (tOE) is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, input hardware reset or to change CE pin from “H” to “L”
6.
Output Disable
With the OE input at a logic high level (VIH) , output from the devices are disabled. This will cause the output
pins to be in a high impedance state.
7.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the
falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to “s AC WRITE CHARACTERISTICS” and Erase/Programming Waveforms for specific timing parameters.
8.
Sector Group Protection
The MBM29DL32TF/BF feature hardware sector group protection. This feature will disable both program and
erase operations in any combination of twenty five sector groups of memory. (See “Sector Group Addresses
Tables (MBM29DL32TF/BF)” in sFLEXIBLE SECTOR-ERASE ARCHITECTURE) . The sector group protection
feature is enabled using programming equipment at the user’s site. The device is shipped with all sector groups
unprotected.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID
= 11.5 V) , CE = VIL and A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector group addresses (A20, A19, A18, A17, A16,
A15, A14, A13, and A12) should be set to the sector to be protected. “Sector Address Tables (MBM29DL32TF/BF)”
in sFLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of the seventy one (71)
individual sectors, and “Sector Group Addresses Tables (MBM29DL32TF/BF)” in sFLEXIBLE SECTOR-ERASE
ARCHITECTURE define the sector group address for each of the twenty five (25) individual group sectors.
Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the
rising edge of the same. Sector group addresses must be held constant during the WE pulse. See “15. Sector
Group Protection Timing Diagram” in sTIMING DIAGRAM and “5. Sector Group Protection Algorithm” in sFLOW
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