- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45202 > MB9BF504RPMC 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120 PDF資料下載
參數(shù)資料
| 型號(hào)： | MB9BF504RPMC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | 16 X 16 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁(yè)數(shù)： | 115/120頁(yè) |
| 文件大?。?/td> | 1277K |
| 代理商： | MB9BF504RPMC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)當(dāng)前第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)
94
8266D-MCU Wireless-06/12
ATmega128RFA1
The register SFD_VALUE contains the one octet start-of-frame delimiter (SFD) to
synchronize to a received frame. It is not recommended to set the low-order 4 bits to 0
due to the way the SHR is formed.
9.8.7 Dynamic Frame Buffer Protection
The ATmega128RFA1 continues the reception of incoming frames as long as it is in
any receive state. When a frame was successfully received and stored into the Frame
Buffer, the following frame will overwrite the Frame Buffer content again. To relax the
timing requirements for a Frame Buffer read access the Dynamic Frame Buffer
Protection prevents that a new valid frame passes to the Frame Buffer until the buffer
protection bit is cleared (RX_SAFE_MODE = 0).
A received frame is automatically protected against overwriting:
in Basic Operating Mode, if its FCS is valid
in Extended Operating Mode, if an TRX24_RX_END interrupt is generated
The Dynamic Frame Buffer Protection is enabled, if register bit RX_SAFE_MODE
(register TRX_CTRL_2, see "TRX_CTRL_2 – Transceiver Control Register 2" on page
114) is set and the radio transceiver state is RX_ON or RX_AACK_ON.
Note that Dynamic Frame Buffer Protection only prevents write accesses from the air
interface not from the application software. The application software may still modify the
Frame Buffer content.
9.8.8 Security Module (AES)
The security module (AES) is characterized by:
Hardware accelerated encryption and decryption;
Compatible with AES-128 standard (128 bit key and data block size);
ECB (encryption/decryption) mode and CBC (encryption) mode support;
Stand-alone operation, independent of other blocks;
Uses 16MHz crystal clock of the transceiver;
9.8.8.1 Overview
The security module is based on an AES-128 core according to the FIPS197 standard
[5]. and provides two modes, the Electronic Code Book (ECB) and the Cipher Block
Chaining (CBC). The security module works independent of other building blocks of the
radio transceiver. Encryption and decryption can be performed in parallel to a frame
transmission or reception.
During radio transceiver SLEEP the registers of the security engine (AES) are cleared
(see section "SLEEP – Sleep State" on page 37).
The ECB and CBC modules including the AES core are clocked with the 16 MHz Radio
Transceiver Crystal Oscillator.
Controlling the security block is possible over 5 Registers within AVR I/O space:
Table 9-24. Security Module Address Space Overview
Register Name
Description
AES_STATUS
AES status register
AES_CTRL
AES control register
AES_KEY
Access to 16 Byte key buffer
AES_STATE
Access to 16 Byte data buffer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB9BF505RPMC | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP120 |
| MB9BF516TBGL | 32-BIT, FLASH, RISC MICROCONTROLLER, PBGA192 |
| MB9BF517TPMC | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP176 |
| MB9BF517SPMC | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP144 |
| MB9BF518TPMC | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP176 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB9BF504RPMC-GE1 | 功能描述:IC MCU 32BIT 256KB FLASH 120LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:FM3 MB9B500 產(chǎn)品培訓(xùn)模塊:MCU Product Line Introduction XMEGA Introduction AVR XMEGA USB Connectivity 標(biāo)準(zhǔn)包裝:90 系列:AVR® XMEGA 核心處理器:AVR 芯體尺寸:8/16-位 速度:32MHz 連通性:I²C，IrDA，SPI，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，DMA，POR，PWM，WDT 輸入/輸出數(shù):50 程序存儲(chǔ)器容量:192KB（96K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:4K x 8 RAM 容量:16K x 8 電壓 - 電源 (Vcc/Vdd):1.6 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 16x12b; D/A 2x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:64-TQFP 包裝:托盤 配用:ATSTK600-RC14-ND - STK600 SOCKET/ADAPTER 64TQFPATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM |
| MB9BF506NABGL-GE1 | 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 112BGA 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 112BGA, Controller Family/Series:ARM Cortex-M3, Core |
| MB9BF506NAPMC-G-JNE1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP, Controller Family/Series:ARM Cortex-M3, Core Size:32bit, No. of I/O's:80, Supply Voltage Min:2.7V, Supply Voltage Max:5.5V, Digital IC Case Style:LQFP, No. of Pins:100, Program Memory Size:512KB, , RoHS Compliant: Yes |
| MB9BF506NBBGL-GE1 | 制造商:FUJITSU 功能描述: |
| MB9BF506NBPMC-G-JNE2 | 制造商:FUJITSU 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。