參數(shù)資料
型號(hào)： MB9BF504NAPMC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù)： 93/108頁
文件大?。?/td> 1298K
代理商： MB9BF504NAPMC
85
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r6.0
MB9B500A Series
(12) I
2C timing
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40
°C to + 85°C )
Typical
mode
High-speed
mode
Parameter
Symbol
Conditions
Min Max Min Max
Unit Remarks
SCL clock frequency
fSCL
0
100
0
400
kHz
(Repeated) START condition
hold time
SDA
↓ → SCL ↓
tHDSTA
4.0
-
0.6
-
μs
SCLclock "L" width
tLOW
4.7
-
1.3
-
μs
SCLclock "H" width
tHIGH
4.0
-
0.6
-
μs
(Repeated) START setup time
SCL
↑ → SDA ↓
tSUSTA
4.7
-
0.6
-
μs
Data hold time
SCL
↓ → SDA ↓ ↑
tHDDAT
0
3.45
(*2)
0
0.9
(*3)
μs
Data setup time
SDA
↓ ↑ → SCL ↑
tSUDAT
250
-
100
-
ns
STOP condition setup time
SCL
↑ → SDA ↑
tSUSTO
4.0
-
0.6
-
μs
Bus free time between
"STOP condition" and
"START condition"
tBUF
CL = 50pF,
R = (Vp/IOL)
(*1)
4.7
-
1.3
-
μs
Noise filter
tSP
-
2 tCYCP
(*4)
-
2 tCYCP
(*4)
-
ns
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL
signal.
*3 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time. Please see the block diagram to refer the APB bus number which I
2C
is connected. To use I2C, set the APB bus clock at 8 MHz or more.
SD
A
SCL
tHDSTA
tLOW
tHDDAT
tSUDAT
tHIGH
tSUSTA
tHDSTA
tSP
tBUF
tSUSTO
DS706-00021-1v0-E
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