參數(shù)資料
型號(hào): MB9BF504NAPMC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù): 21/108頁(yè)
文件大?。?/td> 1298K
代理商: MB9BF504NAPMC
2
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r6.0
MB9B500A Series
FEATURES
32-bit ARM Cortex-M3 Core
Processor version: r2p0
Up to 80MHz Frequency Operation
Memory Protection Unit (MPU): improve the reliability of an embedded system
Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48
peripheral interrupts and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task management
On-chip Memories
[Flash memory]
Up to 512 Kbyte
Read cycle: 0wait-cycle@up to 60MHz, 2wait-cycle* above
*: Instruction pre-fetch buffer is included. So when CPU access continuously, it becomes 0wait-cycle
Security function for code protection
[SRAM]
This series contain a total of up to 64Kbyte on-chip SRAM memories. This is composed of two independent
SRAM(SRAM0, SRAM1). SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core. SRAM1
is connected to System bus.
SRAM0: Up to 32 Kbyte
SRAM1: Up to 32 Kbyte
External Bus Interface
Supports SRAM, NOR& NAND Flash device
Up to 8 chip selects
8/16-bit Data width
Up to 25-bit Address bit
USB Interface
USB interface is composed of Function and Host.
[USB function]
USB2.0 Full-Speed supported
Max. 6 EndPoint supported
EndPoint 0 is control transfer
EndPoint 1 – 5 can be selected bulk-transfer or interrupt-transfer
EndPoint1-5 is comprised Double Buffer
[USB host]
USB2.0 Full/Low speed supported
Bulk-transfer and interrupt-transfer and Isochronous-transfer support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max.256-byte packet-length supported
Wake-up function supported
CAN Interface (Max. 2channels)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
DS706-00021-1v0-E
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