參數(shù)資料
型號: MB9AF112NPMC
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 96/108頁
文件大?。?/td> 1221K
代理商: MB9AF112NPMC
MB9A110 Series
88
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r2.0
(12) I
2C timing
(Vcc = 2.7V to 5.5V, Vss = 0V Ta = - 40
C to + 105C)
Typical
mode
High-speed
mode
Parameter
Symbol
Conditions
Min
Max
Min
Max
Unit Remarks
SCL clock frequency
fSCL
0
100
0
400
kHz
(Repeated) START condition
hold time
SDA
SCL
tHDSTA
4.0
-
0.6
-
μs
SCLclock "L" width
tLOW
4.7
-
1.3
-
μs
SCLclock "H" width
tHIGH
4.0
-
0.6
-
μs
(Repeated) START setup time
SCL
SDA
tSUSTA
4.7
-
0.6
-
μs
Data hold time
SCL
SDA
tHDDAT
0
3.45
(*2)
0
0.9
(*3)
μs
Data setup time
SDA
SCL
tSUDAT
250
-
100
-
ns
STOP condition setup time
SCL
SDA
tSUSTO
4.0
-
0.6
-
μs
Bus free time between
"STOP condition" and
"START condition"
tBUF
CL = 50pF,
R = (Vp/IOL)
(*1)
4.7
-
1.3
-
μs
Noise filter
tSP
-
2 tCYCP
(*4)
-
2 tCYCP
(*4)
-
ns
*1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it doesn't extend at least "L" period (tLOW) of device's SCL
signal.
*3 : A high-speed mode I
2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the peripheral clock cycle time. To use I
2C, set the peripheral bus clock at 8 MHz or more.
SD
A
SCL
tHDSTA
tLOW
tHDDAT
tSUDAT
tHIGH
tSUSTA
tHDSTA
tSP
tBUF
tSUSTO
DS706-00011-0v01-E
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