- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄45201 > MB9AF112NPMC (FUJITSU LTD) 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號(hào)： | MB9AF112NPMC |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 32/108頁(yè) |
| 文件大小： | 1221K |
| 代理商： | MB9AF112NPMC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)
MB9A110 Series
Multi-function Serial Interface (Max. 8channels)
· 4 channels with 16-byte FIFO (ch.4-ch.7), 4 channels without FIFO (ch.0-ch.3)
· Operation mode is selectable from the followings for each channel.
· UART
· CSIO
· LIN
· I2C
[UART]
· Full-duplex double buffer
· Selection with or without parity supported
· Built-in dedicated baud rate generator
· External clock available as a serial clock
· Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)*
· Various error detect functions available (parity errors, framing errors, and overrun errors)
* : MB9AF112L, F114L do not support Hardware Flow control
[CSIO]
· Full-duplex double buffer
· Built-in dedicated baud rate generator
· Overrun error detect function available
[LIN]
· LIN protocol Rev.2.1 supported
· Full-duplex double buffer
· Master/Slave mode supported
· LIN break field generate (can be changed 13-16bit length)
· LIN break delimiter generate (can be changed 1-4bit length)
· Various error detect functions available (parity errors, framing errors, and overrun errors)
[I
2C]
· Standard mode (Max.100kbps) / High-speed mode (Max.400Kbps) supported
DMA Controller (8channels)
DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
· 8 independently configured and operated channels
· Transfer can be started by software or request from the built-in peripherals
· Transfer address area: 32bit(4Gbyte)
· Transfer mode: Block transfer/Burst transfer/Demand transfer
· Transfer data type: byte/half-word/word
· Transfer block count: 1 to 16
· Number of transfers: 1 to 65536
A/D Converter (Max. 16channels)
[12-bit A/D Converter]
· Successive Approximation Register type
· Built-in 3unit*
· Conversion time: 1.0μs@5V
· Priority conversion available (priority at 2levels)
· Scanning conversion mode
· Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4steps)
* : MB9AF112L, F114L built-in 2unit
3
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r1.0
DS706-00011-0v01-E
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB9AF114LPMC | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP64 |
| MB9AF112LPMC1 | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP64 |
| MB9AF115MPMC | 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP80 |
| MB9AF114NPMC | RISC MICROCONTROLLER, PQFP100 |
| MB9AF114LPMC1 | RISC MICROCONTROLLER, PQFP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB9AF114LAPMC1-G-JNE2 | 制造商:Fujitsu 功能描述:Bulk |
| MB9AF114LPMC1-GE1 | 制造商:FUJITSU 功能描述: |
| MB9AF114LPMC1-G-JNE1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 64LQFP |
| MB9AF114MAPMC-G-JNE2 | 制造商:Fujitsu 功能描述:Bulk |
| MB9AF114MPMC-G-JNE1 | 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 80LQFP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。