參數(shù)資料
型號(hào): MB96F326RSBPMC-GSE2
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 7/108頁(yè)
文件大?。?/td> 0K
描述: IC MCU FLASHK/ROM MEMORY 80LQFP
標(biāo)準(zhǔn)包裝: 1
系列: F²MC MB96320
核心處理器: F²MC-16FX
芯體尺寸: 16-位
速度: 56MHz
連通性: CAN,EBI/EMI,I²C,LIN,SCI,UART/USART
外圍設(shè)備: DMA,LVD,LVR,POR,PWM,WDT
輸入/輸出數(shù): 66
程序存儲(chǔ)器容量: 288KB(288K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 12K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 18x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 80-LQFP
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 722 (CN2011-ZH PDF)
其它名稱(chēng): 865-1082
MB96320 Series
104
FME-MB96320 rev 7
■ REVISION HISTORY
Revision
Date
Modication
Prelim 1
2007-05-02
Creation
Prelim 2
2007-05-25
Electrical characteristics updates
Prelim 3
2007-11-23
Cover page: package description removed.
Modication of the block diagram.
Add A pin function group in pin function description.
Electrical characteristics update.
Add chapter on LVD and example characteristics.
In ordering information: typo correction. Persistent instead of persistant.
Memory map relaid out.
Prelim 4
2007-12-20
Update of the block diagram: external bus address lines, clock output
function pins, AVRL removed from ADC block, relayout.
RAMSIZE in RAMSTART table is corrected to 12kB as in described in the
product lineup.
IO map table updated
Ordering information show now PMC packages not PQC. It displays also
the redesigned release.
IO map regenerated
Memory map and Flash conguration reworked
Few typos corrected across the document.
Flash bank renaming.
IO circuit drawings modied.
Prelim 5
2008-02-04
Reload Timer RLT 6 for PPGs added
Block diagram corrected: RLT6 added, OUT10->OUT10_R, TX0/RX0
->RX2/RX2,
Pin assignment: TX3 deleted
Pin function description corrected with all existing pin types
I/O circuit type diagrams corrected
Memory map cleaned up
"Flash sector conguration" replaced by corrected "User ROM Memory
map for Flash devices"
Parallel Flash programming spec removed
IO map table regenerated:
- Port register: Naming style corrected
- Memory control registers renamed (Main -> A)
- addresses after 000BFFh removed
Handling devices: AD converter items added
Absolute maximum ratings: Pd and Ta specied more precisely
Run and Sleep mode currents: more conditions added (1WS settings)
Run mode current spec in 48/24MHz mode corrected
Maximum CLKS1 frequency corrected at 1.8V
External bus timings: missing conditions added and readability improved
Ordering information updated
Typos and formatting corrected
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