參數(shù)資料
型號(hào): MB91FV130CR-ES
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-Bit RISC Microcontroller
中文描述: 32-BIT, 33 MHz, RISC MICROCONTROLLER, CPGA299
封裝: CERAMIC, PGA-299
文件頁數(shù): 38/123頁
文件大?。?/td> 1362K
代理商: MB91FV130CR-ES
MB91133/MB91F133
38
(Continued)
*1 : ICR sets the interruption level for each interruption request using the register built into the interruption controller.
ICR is prepared in accordance with each interruption request.
*2 : TBR is the register that indicates the starting address of the vector table for EIT.
Addresses with added offset values that are specified per TBR and EIT factor will be the vector addresses.
*3 : 0X40, 0X41 interruptions for system codes are used in the event that REALOS/FR is used.
Interruption sauce
Interruption number
Interruption
level
*1
Offset
Address
*2
of TBR default
Decimal Hexadecimal
System reservation
(used under REALOS
*3
)
64
40
2FC
H
000FFEFC
H
System reservation
(used under REALOS
*3
)
65
41
2F8
H
000FFEF8
H
Used under INT instruction
66
42
2F4
H
000FFEF4
H
Used under INT instruction
67
43
2F0
H
000FFEF0
H
Used under INT instruction
68
44
2EC
H
000FFEEC
H
Used under INT instruction
69
45
2E8
H
000FFEE8
H
Used under INT instruction
70
46
2E4
H
000FFEE4
H
Used under INT instruction
71
47
2E0
H
000FFEE0
H
Used under INT instruction
72
48
2DC
H
000FFEDC
H
Used under INT instruction
73
49
2D8
H
000FFED8
H
Used under INT instruction
74
4A
2D4
H
000FFED4
H
Used under INT instruction
75
4B
2D0
H
000FFED0
H
Used under INT instruction
76
4C
2CC
H
000FFECC
H
Used under INT instruction
77
4D
2C8
H
000FFEC8
H
Used under INT instruction
78
4E
2C4
H
000FFEC4
H
Used under INT instruction
79
4F
2C0
H
000FFEC0
H
Used under INT instruction
80
to
255
50
to
FF
2BC
H
to
000
H
000FFEBC
H
to
000FFC00
H
相關(guān)PDF資料
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MB91F133PBT 32-Bit RISC Microcontroller
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MB91F133PMT2 32-Bit RISC Microcontroller
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