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參數(shù)資料
| 型號(hào)： | MB91F492PMC-GE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁(yè)數(shù)： | 44/60頁(yè) |
| 文件大?。?/td> | 1628K |
| 代理商： | MB91F492PMC-GE1 |
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MB91490 Series
DS07-16912-1E
49
(8) I2C Timing
a. Master Mode
(VCC
= 2.7 V to 5.5 V, VSS = AVSS10 = 0.0 V, TA = 40 °C to + 85 °C)
*1 : tCYCP indicates the peripheral clock cycle time.
*2 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT
≥ 250 ns must then be met.
If a device does not extend the “L” period of the SCL signal, it is necessary to output the next piece of data to
the SDA line 1250 ns (SDA and SCL rising Max time + tSUDAT) before the SCL line is released.
*3 : For use at over 100 kHz, set the peripheral clock to at least 6 MHz.
*4 : R and C are the pull-up resistance and load capacitance of the SCL and SDA lines.
Parameter
Sym-
bol
Pin
name
Condition
Standard Mode
Fast Mode*3
Unit
Remarks
Min
Max
Min
Max
SCL clock
frequency
fSCL
SDAn,
SCLn
R=1 k
Ω,
C=50 pF*4
0100
0400
kHz
“L” width of
the SCL clock
tLOW
4.7
1.3
μs
“H” width of the
SCL clock
tHIGH
4.0
0.6
μs
Bus free time
between STOP
and START
conditions
tBUS
4.7
1.3
μs
SCL
↓→
SDA output
delay time
tDLDAT
5
× tCYCP*1
5
× tCYCP*1 ns
Setup time for a
repeated START
condition
SCL
↑→SDA↓
tSUSTA
4.7
0.6
μs
Hold time for a
repeated START
condition
SDA
↓→SCL↓
tHDSTA
4.0
0.6
μs
The first
clock pulse
is generated
after this.
Setup time for
STOP condition
SCL
↑→SDA↑
tSUSTO
4.0
0.6
μs
SDA Data input
hold time
(vs. SCL
↓)
tHDDAT
2
× tCYCP *1
2
× tCYCP *1
μs
SDA Data input
setup time
(vs. SCL
↑)
tSUDAT
250
100 *2
ns
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