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參數(shù)資料
| 型號： | MB91F492PMC-GE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 12 X 12 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 31/60頁 |
| 文件大?。?/td> | 1628K |
| 代理商： | MB91F492PMC-GE1 |
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MB91490 Series
DS07-16912-1E
37
List of pin status
*1 : INITX = “L” : Indicates the pin status with INITX remaining at the “L” level.
*2 : INITX = “H” : Indicates the pin status existing immediately after INITX transition from “L” to “H” level.
Pin name
Function
During initialization
In sleep mode
In stop mode
INITX
= “L”*1
or when
Low voltage
detection
reset occurs
INITX
= “H”*2
or when Low
voltage
detection
reset is
released
HIZ
= 0
HIZ
= 1
NMIX
Input enabled Input enabled
Input enabled
P80 to P83
INT0 to INT3
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Output Hi-Z/
Input “0” fixed
Input enabled
when interrupt
function
selected and
enabled
P84
INT4/PPG4
P85
INT5/PPG5
P86
INT6/PPG6
PA1, PA2
ADTG1,
ADTG2
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PB4 to PB7 AN1-0 to AN1-3
Output Hi-Z/
Input disabled
Output Hi-Z/
Input “0” fixed
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/
Input “0” fixed
PC0 to PC7 AN2-0 to AN2-7
PG0, PG3
SCK0, SCK1
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/In-
put “0” fixed
PG1, PG4
SIN0, SIN1
PG2, PG5
SOT0, SOT1
PH0
SCK2
PH1
SIN2
PH2
SOT2
PJ0, PJ2
TIN0, TIN1
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/In-
put “0” fixed
PJ1, PJ3
TOUT0,
TOUT1
PL0
AIN0
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/In-
put “0” fixed
PL1
BIN0
PL2
ZIN0
PP0 to PP3
IC0 to IC3
Output Hi-Z/
Input disabled
Output Hi-Z/
Input enabled
Retention of the
immediately
prior state
Retention of the
immediately
prior state
Output Hi-Z/In-
put “0” fixed
PP4
CKI0
PP5
DTTI0
PQ0 to PQ5 RTO0 to RTO5
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