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32015G–AVR32–09/09
AT32AP7001
10.8.10
Audio Bitstream DAC
Digital Stereo DAC
Oversampled D/A conversion architecture
– Oversampling ratio fixed 128x
– FIR equalization filter
– Digital interpolation filter: Comb4
– 3rd Order Sigma-Delta D/A converters
Digital bitstream outputs
Parallel interface
Connected to DMA Controller for background transfer without CPU intervention
10.8.11
Timer Counter
Three 16-bit Timer Counter Channels
Wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
Two global registers that act on all three TC Channels
10.8.12
Pulse Width Modulation Controller
4 channels, one 16-bit counter per channel
Common clock generator, providing Thirteen Different Clocks
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
Independent channel programming
– Independent Enable Disable Commands
– Independent Clock
– Independent Period and Duty Cycle, with Double Bufferization
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform