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參數(shù)資料
型號(hào): MB91F479PMC1-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 83/94頁(yè)
文件大?。?/td> 0K
描述: IC MCU 512KB FLASH 144-LQFP
標(biāo)準(zhǔn)包裝: 1
系列: FR MB91470
核心處理器: FR60 RISC
芯體尺寸: 32-位
速度: 80MHz
連通性: EBI/EMI,I²C,F(xiàn)IFO,SIO
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 113
程序存儲(chǔ)器容量: 512KB(512K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 32K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x8/10b,4x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
配用: 865-1109-ND - KIT 32BIT RSC MCU MOTOR CONTROL
其它名稱: 865-1095
86
32015G–AVR32–09/09
AT32AP7001
10.8
Peripheral overview
10.8.1
External Bus Interface
Optimized for Application Memory Space support
Integrates Three External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
– ECC Controller
Additional Logic for NAND Flash/SmartMediaTM and CompactFlashTM Support
– SmartMedia support: 8-bit as well as 16-bit devices are supported
– CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are
supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode)
are not handled.
Optimized External Bus:
– 16- or 32-bit Data Bus
– Up to 26-bit Address Bus, Up to 64-Mbytes Addressable
– Optimized pin multiplexing to reduce latencies on External Memories
Up to 6 Chip Selects, Configurable Assignment:
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash/SmartMediaTM Support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlashTM Support
10.8.2
Static Memory Controller
6 Chip Selects Available
64-Mbyte Address Space per Chip Select
8-, 16- or 32-bit Data Bus
Word, Halfword, Byte Transfers
Byte Write or Byte Select Lines
Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select
Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select
Programmable Data Float Time per Chip Select
Compliant with LCD Module
External Wait Request
Automatic Switch to Slow Clock Mode
Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes
10.8.3
SDRAM Controller
Numerous Configurations Supported
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with Two or Four Internal Banks
– SDRAM with 16- or 32-bit Data Path
Programming Facilities
– Word, Half-word, Byte Access
– Automatic Page Break When Memory Boundary Has Been Reached
– Multibank Ping-pong Access
– Timing Parameters Specified by Software
– Automatic Refresh Operation, Refresh Rate is Programmable
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