參數(shù)資料
型號(hào): MB91F475PMC1-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 66/94頁(yè)
文件大小: 0K
描述: IC MCU 256KB FLASH 144-LQFP
標(biāo)準(zhǔn)包裝: 1
系列: FR MB91470
核心處理器: FR60 RISC
芯體尺寸: 32-位
速度: 80MHz
連通性: EBI/EMI,I²C,F(xiàn)IFO,SIO
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 113
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x8/10b,4x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
其它名稱: 865-1093
70
32015G–AVR32–09/09
AT32AP7001
8.9
Data Hazards
Data hazards are caused by data dependencies between instructions which are in different
stages of the pipeline and reads/writes registers which are common to several pipeline stages.
Because of the 3-stage pipeline employed in the PICO data hazards might exist between
instructions. Data hazards are handled by hardware interlocks which can stall a new read com-
mand from or write command to the PICO register file.
Table 8-5.
Data Hazards
Instruction
Next
Instruction
Condition
Stall
Cycles
picovmul
picovmac
picosvmul
picosvmac
picomv.x Pr,...
picold.x
picoldm
Write-After-Read (WAR) or Write-After-Write (WAW)
Hazard will occur if writing COEFFn_A/B, VMUn_OUT
or CONFIG since these are accessed when the PICO
command is in Pipeline Stage 2 and Pipeline Stage 3.
1
Writes to INPIXn registers produces no hazard since
they are only accessed in Pipeline Stage 1.
0
picomv.x Rd,...
picost.x
picostm
Read-After-Write Hazard (RAW) will occur if reading
the PICO register file while a command is in the
pipeline.
2
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