參數(shù)資料
型號(hào): MB91F475PMC1-GE1
廠商: Fujitsu Semiconductor America Inc
文件頁(yè)數(shù): 40/94頁(yè)
文件大?。?/td> 0K
描述: IC MCU 256KB FLASH 144-LQFP
標(biāo)準(zhǔn)包裝: 1
系列: FR MB91470
核心處理器: FR60 RISC
芯體尺寸: 32-位
速度: 80MHz
連通性: EBI/EMI,I²C,F(xiàn)IFO,SIO
外圍設(shè)備: DMA,PWM,WDT
輸入/輸出數(shù): 113
程序存儲(chǔ)器容量: 256KB(256K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x8/10b,4x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 144-LQFP
包裝: 托盤
其它名稱: 865-1093
47
32015G–AVR32–09/09
AT32AP7001
8.7.1.16
PICO Configuration Register
Register Name: CONFIG
Access Type: Read/Write
OIM: Output Insertion Mode
The OIM bit specifies the semantics of the OUTd output pixel address parameter to the pico(s)v(mul/mac) instructions. The
OIM together with the output pixel address parameter specify which of the 12 output bytes (OUTn) of the OUTPIXn regis-
ters will be updated with the results from the VMUs. Table 8-2 on page 47 describes the different Output Insertion Modes.
See Section 8.6 ”O(jiān)utput Pixel Inserter” on page 29 for a description of the Output Pixel Inserter.
ISM: Input Selection Mode
The ISM fie l d sp ec ifies th e se m a n t ics o f th e inp u t p i xe l ad dr e ss p a r a m e t e r s INx , INy an d I N z to th e
pico(s)v(mul/mac) instructions. Together with the three input pixel addresses the ISM field specifies to the Input Pixel
Selector which of the input pixels (INn) that should be selected as inputs to the VMUs.Table 8-3 on page 48 describes the
31
30
29
28
27
26
25
24
--------
23
22
21
20
19
18
17
16
--------
15
14
13
12
11
10
9
8
-----
OIM
ISM
76543210
OFFSET_FRAC_BITS
COEFF_FRAC_BITS
Table 8-2.
Output Insertion Modes
OIM
Mode
Description
0
Packed Insertion Mode
{OUTPIX0, OUTPIX1, OUTPIX2} is treated as one large register containing 4 sequential 24-
bit pixel triplets. The DST_ADR field specifies which of the sequential triplets will be updated.
OUT(d*3 + 0)
← Scaled and saturated output from VMU0
OUT(d*3 + 1)
← Scaled and saturated output from VMU1
OUT(d*3 + 2)
← Scaled and saturated output from VMU2
1
Planar Insertion Mode
Each of the OUTPIXn registers will get one of the resulting pixels. The triplet address
specifies what byte in each of the OUTPIXn registers the results will be written to.
OUT(d + 0)
← Scaled and saturated output from VMU0
OUT(d+ 4)
← Scaled and saturated output from VMU1
OUT(d + 8)
← Scaled and saturated output from VMU2
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