參數(shù)資料
型號： MB91637APMC
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, MROM, 40 MHz, RISC MICROCONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù)： 49/136頁
文件大?。?/td> 4123K
代理商： MB91637APMC
MB91635A Series
2
DS07-16909-2E
- Interrupts (save PC and PS) : 6 cycles, 16 priority levels
- Harvard architecture allowing program access and data access to be executed simultaneously
- Instruction prefetch function has been added with 4 word instruction queue of CPU
Instruction compatible with FR family CPU
- Additional bit search instructions
- No resource instructions and coprocessor instructions
Maximum operating frequency
CPU : 60 MHz
Resources : 40 MHz
External bus : 40 MHz
Note: The PLL clock specification of MB91635A series
In MB91635A series, PLL clock specification has been modified from MB91635 series. The setting of dividing
by 1 of PLL macro oscillation clock divide configuration value is prohibited.
Therefore, please use the device with setting as dividing by 2 to 4 by ODS0 or ODS1 bit in the PLL config-
uration register (PLLCR). For more details, refer to “4.4.4 PLL Configuration Register (PLLCR)” in the
“Hardware Manual”.
External bus interface
Operating frequency : Max 40 MHz
24 address lines, 8- or 16-bit data I/O (separate busses or multiplexed bus)
Chip select output available for 4 independent programmable areas
Programmable automatic wait cycle insertion for each area
DMA controller (DMAC)
8 channels
Address space : 32 bits (4 Gbytes)
Transfer modes : Block transfer/burst transfer/demand transfer
Address update : Increment/decrement/fixed (increment/decrement step size of 1, 2, or 4)
Transfer data length : Selectable from 8-bit, 16-bit, 32-bit
Block size : 1 to 16
Number of transfers : 1 to 65535
Transfer requests
- Requests from software
- Interrupt requests from peripheral resources (interrupt requests are shared, including external interrupts)
- Requests from external pins
Reload functions : Reload can be specified on all channels
Priority order : Fixed (ch.0 > ch.1 > ch.2 > ch.3 > ...) or round-robin
Interrupt requests : Interrupts can be generated for transfer complete, transfer error, and transfer interrupted.
(Continued)
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