參數(shù)資料
型號: MB89PV630C-SH
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 10 MHz, MICROCONTROLLER, CDIP64
封裝: CERAMIC, MDIP-64
文件頁數(shù): 84/153頁
文件大?。?/td> 7326K
代理商: MB89PV630C-SH
HARDWARE CONFIGURATION
2-13
RDY is an signal to execute the Ready function. When a Low level is input for RDY, the bus cycle is pro-
longed in CLK cycle. Fetching is carried out near the rising edge of the CLK signal. To prolong the bus
cycle, set the RDY signal to Low before the rising edge of the CLK signal. When the ready function is not
used in the external bus mode, the RDY pin should be pulled up.
The HRQ and HAK signals are used for the hold function. To obtain the external bus, set the HRQ signal to
High. After that, the CPU recognizes the bus request between instructions to stop operation and sets the
HAK signal to Low after waiting one half cycle. It signals the outside that the bus is open in this way. When
another device terminates use of the bus, set the HRQ signal to Low to notify the CPU. When the CPU
detects the Low level of the HRQ signal, it sets the HAK signal to High and starts using the external bus
after waiting one half cycle. The hold function timing concept is diagram shown below.
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