參數(shù)資料
型號: MB89PV630C-SH
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 10 MHz, MICROCONTROLLER, CDIP64
封裝: CERAMIC, MDIP-64
文件頁數(shù): 34/153頁
文件大?。?/td> 7326K
代理商: MB89PV630C-SH
MB89630 SERIES HARDWARE MANUAL
3-10
3.5 READY AND HOLD FUNCTIONS
3.5.1 Ready Function
The RDY pin allows access to the low-speed memory and resources. When the RDY pin goes Low while
the CPU is conducting external access, the CPU prolongs the last bus cycle by double oscillations. When
the CPU conducts an internal access, the value of the RDY pin is ignored. As shown in Figure 3.7, the
Ready signal is input near the center of the RD or WR pin. In the not-ready state, the Ready signal is input
around the CLK rising edge. The Ready/Not-ready signal can be generated in the circuit as shown in Fig-
ure 3.8.
Note: The read cycle is also prolonged in the same manner.
Fig. 3.21 Ready Input Timing Chart (Write Cycle)
Fig. 3.22 Ready Generation Circuit
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