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參數(shù)資料
| 型號(hào)： | MB89P637-SH |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | SHRINK, DIP-64 |
| 文件頁(yè)數(shù)： | 90/153頁(yè) |
| 文件大小： | 7326K |
| 代理商： | MB89P637-SH |
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MB89630 SERIES HARDWARE MANUAL
2-18
[1] WATCH mode
Switching to WATCH mode
Writing 1 at the TMD bit (bit 3) of the STBC register switches the mode to WATCH mode. Writing is
invalid if 1 is set at the SCS bit (bit 2) of the SYCC register.
The WATCH mode stops all chip functions except the watch prescaler, external interrupt, and wake-up
functions. Therefore, data can be held with the lowest power consumption.
The input/output pins and output pins during the WATCH mode can be controlled by the SPL bit of the
STBC register so that they are held in the state immediately before entering the WATCH mode or so
that they enter the high-impedance state.
If an interrupt is requested when 1 is written at the TMD bit , instruction execution continues without
switching to the WATCH mode.
In the WATCH mode, the values of registers and RAM immediately before entering the WATCH mode
are held.
Canceling WATCH mode
The WATCH mode is canceled by inputting the reset signal and requesting an interrupt.
When the reset signal is input during the WATCH mode, the CPU is switched to the reset state and the
WATCH mode is canceled.
When an interrupt higher than level 11 is requested from a resource during the WATCH mode, the
WATCH mode is canceled.
When the I flag and IL bit are enabled like an ordinary interrupt after canceling, the CPU executes the
interrupt processing. When they are disabled, the CPU executes the interrupt processing from the
instruction next to the one before entering the WATCH mode.
If the WATCH mode is canceled by inputting the reset signal, the CPU is switched to the oscillation
stabilization wait state. Therefore, the reset sequence is not executed unless the oscillation stabi liza-
tion time is elapsed. The oscillation stabilization time will be that of the main clock selected by the
WT1 and WT0 bits. However, when Power-on Reset is not specified by the mask option, the CPU is
not switched to the oscillation stabilization wait state, even if the WATCH mode is canceled by inputting
the reset signal.
[2] SLEEP mode
Switching to SLEEP mode
Writing 1 at the SLP bit (bit 6) of the STBC register switches the mode to SLEEP mode.
The SLEEP mode stops the CPU operating clock pulse; only the CPU stops and the resources con-
tinue to operate.
If an interrupt is requested when 1 is written at the SLP bit (bit 6), instruction execution continues with-
out switching to the SLEEP mode. In the SLEEP mode,the values of registers and RAM im mediately
before entering the SLEEP mode are held.
Canceling SLEEP mode
The SLEEP mode is canceled by inputting the reset signal and requesting an interrupt.
When the reset signal is input during the SLEEP mode, the CPU is switched to the reset state and the
SLEEP mode is canceled.
When an interrupt higher than level 11 is requested from a resource during the SLEEP mode, the
SLEEP mode is canceled.
When the I flag and IL bit are enabled like an ordinary interrupt after canceling, the CPU executes the
interrupt processing. When they are disabled, the CPU executes the interrupt processing from the
instruction next to the one before entering the SLEEP mode.
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