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參數資料
| 型號： | MB88R157PNF-G-JN-EFE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 134 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 5.05 X 3.90 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-8 |
| 文件頁數： | 21/24頁 |
| 文件大?。?/td> | 724K |
| 代理商： | MB88R157PNF-G-JN-EFE1 |
MB88R157
6
DS04-29132-3E
■ MEMORY MAP
Address
Function
Remarks
bit0-bit11
M divider setting (12-bit)
Selectable in the range of 1 to 4096
bit12-bit22
N divider setting (11-bit)
Selectable in the range of 1 to 2048
bit23-bit29
K divider setting (7-bit)
Selectable in the range of 1 to 128
bit30-bit32
L divider setting (3-bit)
Modulation frequency setting
(the value is due to the input frequency)
bit33-bit36
Charge Pump setting (4-bit)
Charge pump current setting due to VCO oscillation frequency
bit37-bit41
VCO Gain setting (5-bit)
VCO gain setting due to VCO oscillation frequency
bit42-bit44
Modulation rate setting (3-bit)
No modulation,
±0.25%, ±0.50%, ±0.75%, ±1.00%, ±1.25%,
±1.50%, ±1.75% are selectable
bit45
OUT pin setting (1bit)
Selectable OUT pin situation at OE pin
= L
0 : L output 1 : Hi-Z output
bit46
Output drive setting (1bit)
OUT pin driving ability setting
0 : Ability small 1 : Ability large
bit47
Source clock dividing mode (1bit)
Source clock selectable to K divider
0 : VCO output 1 : Source clock
bit48
PLL mode setting (1bit)
0 : Normal mode 1 : PLL mode
bit49-bit55
XIN oscillation stabilization
capacitance setting (7-bit)
Capacitance is selectable from 5 pF to 10 pF by 0.039 pF Step
bit56-bit62
XOUT oscillation stabilization
capacitance setting (7-bit)
Capacitance is selectable from 5 pF to 10 pF by 0.039 pF Step
bit63
Reserve
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參數描述 |
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