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參數(shù)資料
| 型號(hào)： | MB88R157PNF-G-JN-EFE1 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 134 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | 5.05 X 3.90 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-8 |
| 文件頁(yè)數(shù)： | 2/24頁(yè) |
| 文件大小： | 724K |
| 代理商： | MB88R157PNF-G-JN-EFE1 |
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MB88R157
10
DS04-29132-3E
pa
■ MEMORY ACCESS
Read/write to the built-in non-volatile memory is enabled through the serial communication with the OE pin
functioned as the I/O pin.
Set for the communication protocol. Also, set the transfer speed as 1/512 of the source clock.
Asynchronous transfer mode of UART
LSB fast
NRZ format
Bit length: 8 bits
No parity
Stop bit: 1 bit
1. Set the PEX pin to “L” more than 30 ms after this device is turned on, input a command from the OE pin set
MB88R157 into memory access mode.(When a command is input by serial communication, data of “FDH” is
sent.)
Note:
When memory access is available, source clock can be output from the OUT pin.
Fix the PEX pin to “H”, or fix the OE pin to “H” or “L” until command input.
2. At writing, “00H” is sent serially, and at reading, “40H” is sent.
Note: This device needs to stop outputting to the OE pin of the transferred device within 15
μs after transferring
“40H” serially at the reading state and place it to a receivable state.
3. At writing : Send 8-byte data blocks from the lower address of the memory map in turn with more than 100
μs
between each data block.
At read
: This device outputs 8-byte data blocks from the lower address of the memory map in turn.
4. Repeat the operations of 2. and 3. for re-writing and re-reading.
To operate the device using the written data, turn on the power again.
However, the oscillation stabilization capacitance is set simultaneously with writing to memory. When the
oscillation stabilization capacitance and the crystal oscillation frequency are adjusted, change the oscillation
stabilization capacitance value so that the clock output from the OUT pin is set to the desired frequency.
VDD
OE
30 ms
2.5 V
OUT
PEX
Memory access
mode signal
(internal)
Source clock output
Transfer sequence
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