參數(shù)資料
型號(hào)： MB8117800A-60
廠商： Electronic Theatre Controls, Inc.
英文描述： 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
中文描述： 2的MX 8位快速頁(yè)面模式動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù)： 5/27頁(yè)
文件大?。?/td> 580K
代理商： MB8117800A-60
5
MB8117800A-60/-70
I
FUNCTIONAL TRUTH TABLE
X; “H” or “L”
*; It is impossible in Fast Page Mode.
I
FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty-one input bits are required to decode any eight of 16,777,216 cell addresses in the memory matrix.
Since only eleven address bits (A0 to A10) are available, the row and column inputs are separately strobed by
RAS and CAS as shown in Figure 1. First, eleven row address bits are input on pins A0-through-A10 and latched
with the row address strobe (RAS) then, ten column address bits are input and latched with the column address
strobe (CAS). Both row and column addresses must be stable on or before the falling edge of RAS and CAS,
respectively. The address latches are of the flow-through type; thus, address information appearing after t
RAH
(min) + t
T
is automatically treated as the column address.
WRITE ENABLE
The read or write mode is determined by the logic state of WE. When WE is active Low, a write cycle is initiated;
when WE is High, a read cycle is selected. During the read mode, input data is ignored.
DATA INPUTS
Input data is written into memory in either of three basic ways-an early write cycle, an OE (delayed) write cycle,
and a read-modify-write cycle. The falling edge of WE or CAS, whichever is later, serves as the input data-latch
strobe. In an early write cycle, the input data (DQ
1
-DQ
8
) is strobed by CAS and the setup/hold times are referenced
to CAS because WE goes Low before CAS. In a delayed write or a read-modify-write cycle, WE goes Low after
CAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal.
Operation Mode
Clock Input
Address
Input Data
Refresh
Note
RAS
CAS
WE
OE
Row
Column
Input
Output
Standby
H
H
X
X
—
—
—
High-Z
—
Read Cycle
L
L
H
L
Valid
Valid
—
Valid
Yes*
t
RCS
≥
t
RCS
(min)
Write Cycle
(Early Write)
L
L
L
X
Valid
Valid
Valid
High-Z
Yes*
t
WCS
≥
t
WCS
(min)
Read-Modify-
Write Cycle
L
L
H
→
L
L
→
H
Valid
Valid
Valid
Valid
Yes*
RAS-only
Refresh Cycle
L
H
X
X
Valid
—
—
High-Z
Yes
CAS-before-
RAS Refresh
Cycle
L
L
X
X
—
—
—
High-Z
Yes
t
CSR
≥
t
CSR
(min)
Hidden Refresh
Cycle
H
→
L
L
H
→
X
L
—
—
—
Valid
Yes
Previous data is
kept.
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