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參數(shù)資料
| 型號： | MB8117800A-60 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM |
| 中文描述： | 2的MX 8位快速頁面模式動(dòng)態(tài)隨機(jī)存儲器 |
| 文件頁數(shù)： | 23/27頁 |
| 文件大小： | 580K |
| 代理商： | MB8117800A-60 |
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23
MB8117800A-60/-70
A
0
to A
10
CAS
V
IH
V
IL
V
OH
V
OL
RAS
V
IH
V
IL
V
IH
V
IL
DQ
(Output)
Fig. 16 – CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
WE
V
IH
V
IL
OE
V
IH
V
IL
V
IH
V
IL
DQ
(Input)
t
CRP
“H” or “L”
COLUMN ADDRESSES
Valid Data
HIGH-Z
HIGH-Z
VALID DATA IN
HIGH-Z
t
RCD
t
CP
t
FRSH
t
FCAS
t
RP
t
FCAH
t
ASC
t
RCS
t
CWL
RWL
t
FCWD
t
FCAC
t
DS
t
DZC
t
WP
t
DH
t
OED
t
DZO
t
OEH
t
ON
t
OEA
t
OEZ
DESCRIPTION
A special timing sequence using the CAS-before-RAS refresh counter test cycle provides a convenient method to verify the function
of CAS-before-RAS refresh circuitry. If, a CAS-before-RAS refresh cycle CAS makes a transition from High to Low while RAS is
held Low, read and write operations are enabled as shown above. Row and column addresses are defined as follows:
Row Address: Bits A0 through A10 are defined by the on-chip refresh counter.
Column Address: Bits A0 through A9 are defined by latching levels on A0-A9 at the second falling edge of CAS.
The CAS-before-RAS Counter Test procedure is as follows ;
1) Initialize the internal refresh address counter by using 8 RAS-only refresh cycles.
2) Use the same column address throughout the test.
3) Write “0” to all 2048 row addresses at the same column address by using normal write cycles.
4) Read “0” written in procedure 3) and check; simultaneously write “1” to the same addresses by using CAS-
before-RAS refresh counter test (read-modify-write cycles). Repeat this procedure 2048 times with addresses
generated by the internal refresh address counter.
5) Read and check data written in procedure 4) by using normal read cycle for all 2048 memory locations.
6) Reverse test data and repeat procedures 3), 4), and 5).
MB817800A-70
Min
.
—
MB817800A-60
Min.
—
Unit
Parameter
Max.
55
—
—
—
—
ns
No
.
Max.
50
—
—
—
—
90
91
92
93
94
Symbol
(At recommended operating conditions unless otherwise noted.)
CAS to WE Delay Time
CAS Pulse Width
RAS Hold Time
35
77
99
99
ns
35
70
90
90
Column Address Hold Time
ns
ns
ns
Access Time from CAS
t
FCAC
t
FCAH
t
FCWD
t
FCAS
t
FRSH
Note: Assumes that CAS-before-RAS refresh counter test cycle only.
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