參數(shù)資料
型號: MAXQ618J-0000+
廠商: Maxim Integrated Products
文件頁數(shù): 13/26頁
文件大?。?/td> 0K
描述: IC MCU 16BIT 80KB FLASH 44TQFN
產(chǎn)品培訓模塊: Obsolescence Mitigation Program
標準包裝: 43
系列: MAXQ®
核心處理器: RISC
芯體尺寸: 16-位
速度: 12MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,紅外線,電源故障,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 80KB(80K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.6 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 44-WFQFN 裸露焊盤
包裝: 管件
MAXQ618
16-Bit Microcontroller with Infrared Module
20
Maxim Integrated
Operating Modes
The lowest power mode of operation is stop mode. In this
mode, CPU state and memories are preserved, but the
CPU is not actively running. Wake-up sources include
external I/O interrupts, the power-fail warning interrupt,
wake-up timer, or a power-fail reset. Any time the micro-
controller is in a state where code does not need to be
executed, the user software can put the device into stop
mode. The nanopower ring oscillator is an internal ultra-
low-power (400nA) 8kHz ring oscillator that can be used
to drive a wake-up timer that exits stop mode. The wake-
up timer is programmable by software in steps of 125Fs
up to approximately 8s.
The power-fail monitor is always on during normal opera-
tion. However, it can be selectively disabled during stop
mode to minimize power consumption. This feature is
enabled using the power-fail monitor disable (PFD) bit
in the PWCN register. The reset default state for the PFD
bit is 1, which disables the power-fail monitor function
during stop mode. If power-fail monitoring is disabled
(PFD = 1) during stop mode, the circuitry responsible
for generating a power-fail warning or reset is shut down
and neither condition is detected. Thus, the VDD < VRST
condition does not invoke a reset state.
Power-Fail Detection
Figures 10, 11, and 12 show the power-fail detection and
response during normal and stop-mode operation. If a
reset is caused by a power-fail, the power-fail monitor
can be set to one of the following intervals:
Alwayson—continuousmonitoring
211 nanopower ring oscillator clocks (~256ms)
212 nanopower ring oscillator clocks (~512ms)
213 nanopower ring oscillator clocks (~1.024s)
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
nanopower ring-oscillator cycles. If VDD > VRST during
detection, VDD is monitored for an additional nanopower
ring-oscillator period. If VDD remains above VRST for the
third nanopower ring period, the CPU exits the reset state
and resumes normal operation from utility ROM at 8000h
after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watch-
dog timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the CPU
exits the reset state in less than 20 crystal cycles after the
reset source is removed.
Figure 10. Power-Fail Detection During Normal Operation
A
B
C
D
F
G
H
I
E
VDD
VPFW
VRST
VPOR
INTERNAL RESET
(ACTIVE HIGH)
t
< tPFW
t
≥ tPFW
t
≥ tPFW
t
≥ tPFW
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參數(shù)描述
MAXQ618J-0000+ 功能描述:16位微控制器 - MCU 16-Bit MCU w/Infrared Module RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數(shù)據(jù)總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT
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