參數(shù)資料
型號(hào): MAX9867EWV+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 35/55頁(yè)
文件大小: 0K
描述: IC STEREO AUD CODEC LP 30WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 立體聲音頻
數(shù)據(jù)接口: I²C,串行
分辨率(位): 18 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 85 / 90
電壓 - 電源,模擬: 1.65 V ~ 1.95 V
電壓 - 電源,數(shù)字: 1.65 V ~ 1.95 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 30-WFBGA,WLBGA
供應(yīng)商設(shè)備封裝: 30-WLP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): MAX9867EWV+TDKR
MAX9867
Ultra-Low Power Stereo Audio Codec
40
______________________________________________________________________________________
ADC
The MAX9867 includes two 16-bit ADCs. The first ADC
is used to record left-channel microphone and line-input
audio signals. The second ADC can be used to record
right-channel microphone and line-input signals, or it
can be configured to accurately measure DC voltages.
When measuring DC voltages, both the left and right
ADCs must be enabled by setting ADLEN and ADREN
in register 0x17. The input to the second ADC is JACK-
SNS/AUX and the output is reported in AUX (registers
0x02 and 0x03). Since the audio ADC is used to per-
form the measurement, the digital audio interface must
be properly configured. If the left ADC is being used to
convert audio, the DC measurement is performed at the
same sample rate. When not using the left ADC, config-
ure the digital interface for a 48kHz sample rate to
ensure the fastest possible settling time.
To ensure accurate results, the MAX9867 includes two
calibration routines. Calibrate the ADC each time the
MAX9867 is powered on. Calibration settings are not
lost if the MAX9867 is placed in shutdown. When mak-
ing a measurement, set AUXCAP to 1 to prevent AUX
from changing while reading the registers.
Setup Procedure
1) Ensure a valid MCLK signal is provided and config-
ure PSCLK appropriately.
2) Choose a clocking mode. The following options are
possible:
Slave mode with LRCLK and BCLK signals pro-
vided. The measurement sample rate is deter-
mined by the external clocks.
Slave mode with no LRCLK and BCLK signals
provided. Configure the device for normal clock
mode using the NI ratio. Select fS = 48kHz to allow
for the fastest settling times.
Master mode with audio. Configure the device in
normal mode using the NI ratio or exact integer
mode using FREQ as required by the audio signal.
Master mode without audio. Configure the
device in normal mode using the NI ratio. Select fS
= 48kHz to allow for the fastest settling times.
3) Ensure JACKSNS is disabled.
4) Enable the left and right ADC; take the MAX9867 out
of shutdown.
Offset Calibration Procedure
Perform the following steps before the first DC mea-
surement is taken after applying power to the
MAX9867:
1) Enable the AUX input (AUXEN = 1).
2) Enable the offset calibration (AUXCAL = 1).
3) Wait the appropriate time (see Table 13).
4) Complete calibration (AUXCAL = 0).
Gain Calibration Procedure
Perform the following steps the first time a DC measure-
ment is taken after applying power to the MAX9867 or if
the temperature changes significantly:
1) Enable the AUX input (AUXEN = 1).
2) Start gain calibration (AUXGAIN = 1).
3) Wait the appropriate time (see Table 13).
4) Freeze the measurement results (AUXCAP = 1).
5) Read AUX and store the value in memory to correct
all future measurements (k = AUX[15:0], k is typical-
ly 19500).
6) Complete calibration (AUXGAIN = AUXCAP = 0).
DC Measurement Procedure
Perform the following steps after offset and gain cali-
bration are complete:
1) Enable the AUX input (AUXEN = 1).
2) Wait the appropriate time (see Table 13).
3) Freeze the measurement results (AUXCAP = 1).
4) Read AUX and correct with the gain calibration
value:
5) Complete measurement (AUXCAP = 0).
V
AUX
k
AUX =
0 738
15 0
.
[: ]
Table 13. AUX ADC Wait Times
WAIT TIMES
LRCLK (kHz)
WAIT TIME (ms)
48
40
44.1
44
32
60
24
80
22.05
90
16
120
12
160
11.025
175
8
240
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