參數(shù)資料
型號(hào)： MAX9867EWV+T
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 19/55頁(yè)
文件大小： 0K
描述： IC STEREO AUD CODEC LP 30WLP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 立體聲音頻
數(shù)據(jù)接口： I²C，串行
分辨率（位）： 18 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 85 / 90
電壓 - 電源，模擬： 1.65 V ~ 1.95 V
電壓 - 電源，數(shù)字： 1.65 V ~ 1.95 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 30-WFBGA，WLBGA
供應(yīng)商設(shè)備封裝： 30-WLP
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： MAX9867EWV+TDKR
MAX9867
Ultra-Low Power Stereo Audio Codec
26
______________________________________________________________________________________
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
REGISTER
ADDRESS
Interface Mode
MAS
WCI
BCI
DLY
HIZOFF
TDM
0
0x08
Interface Mode
0
LVOLFIX
DMONO
BSEL
0x09
BITS
FUNCTION
MAS
Master Mode
0 = The MAX9867 operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9867 operates in master mode with LRCLK and BCLK configured as outputs.
WCI
LRCLK Invert
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
Note: WCI is ignored when TDM = 1.
BCI
BCLK Invert
In master and slave modes:
0 = SDIN is latched into the part on the rising edge of BCLK.
SDOUT transitions after the rising edge of BCLK as determined by SDODLY.
1 = SDIN is latched into the part on the falling edge of BCLK.
SDOUT transitions after the falling edge of BCLK as determined by SDODLY.
In master mode:
0 = LRCLK changes state immediately after the rising edge of BCLK.
1 = LRCLK changes state immediately after the falling edge of BCLK.
SDODLY
SDOUT Delay
0 = SDOUT transitions one half BCLK cycle after SDIN is latched into the part.
1 = SDOUT transitions on the same BCLK edge as SDIN is latched into the part.
See Figures 1–4 for complete details. See Register 0x04 (interrupt registers).
DLY
Delay Mode
0 = SDIN/SDOUT data is latched on the first BCLK edge following an LRCLK edge.
1 = SDIN/SDOUT data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge
following an LRCLK edge (I
2S-compatible mode).
Note: DLY is ignored when TDM = 1.
HIZOFF
SDOUT High-Impedance Mode
0 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the MAX9867,
allowing SDOUT to be shared by other devices.
1 = SDOUT is set either high or low after all data bits have been transferred out of the MAX9867.
Note: High-impedance mode is intended for use when TDM = 1.
LVOLFIX
See the Line Inputs section.
Table 6. Digital Audio Interface Registers
Digital Audio Interface
The MAX9867’s digital audio interface supports a wide
range of operating modes to ensure maximum compati-
bility. See Figures 1–4 for timing diagrams. In master
mode, the MAX9867 outputs LRCLK and BCLK, while in
slave mode they are inputs. When operating in master
mode, BCLK can be configured in a number of ways to
ensure compatiblity with other audio devices.
LVOLFIX is used to fix the line input playback volume to
0dB regardless of VOLL and VOLR. See the
Line Inputs
section for complete details and Table 6.
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MAX986ESA 功能描述:校驗(yàn)器 IC Single uPower Comparator RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類(lèi)型: 通道數(shù)量: 輸出類(lèi)型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel
MAX986ESA+ 功能描述:校驗(yàn)器 IC Single uPower Comparator RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類(lèi)型: 通道數(shù)量: 輸出類(lèi)型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel
MAX986ESA+T 功能描述:校驗(yàn)器 IC Single uPower Comparator RoHS:否 制造商:STMicroelectronics 產(chǎn)品: 比較器類(lèi)型: 通道數(shù)量: 輸出類(lèi)型:Push-Pull 電源電壓-最大:5.5 V 電源電壓-最小:1.1 V 補(bǔ)償電壓（最大值）:6 mV 電源電流（最大值）:1350 nA 響應(yīng)時(shí)間: 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SC-70-5 封裝:Reel
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MAX986EUK 制造商:Maxim Integrated Products 功能描述:- Rail/Tube
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