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參數(shù)資料
| 型號： | MAX9851EVCMODU |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 編解碼器 |
| 英文描述： | MAX9851評估板/評估系統(tǒng) |
| 中文描述： | PCM CODEC |
| 文件頁數(shù)： | 55/73頁 |
| 文件大?。?/td> | 1357K |
| 代理商： | MAX9851EVCMODU |
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MAX9851/MAX9853
Stereo Audio CODECs with Microphone, DirectDrive
Headphones, Speaker Amplifiers, or Line Outputs
______________________________________________________________________________________
59
Table 39. System Bit Descriptions
System Control Register (0x1A)
REG
B7
B6
B5
B4
B3
B2
B1
B0
0x1A
SHDN
HFEN
LFEN
CPEN
0
1
0
CPCLK
Headset Detect Enable (ENA)
1 = Enabled.
0 = Disabled.
ENA = 1 enables the headphone sense biases and
powers on the threshold comparator circuitry.
Headphone amplifiers must be disabled and micro-
phone amplifiers and bias resistors must be enabled
for proper headset detection. ENA = 0 powers down
the circuitry and sets HSDET (register 0x01, bits
B5–B0) to 0x00.
Headset Detect Low-Power Mode (SLEEP)
1 = Enabled.
0 = Disabled.
SLEEP = 1 places the detection circuitry in low-power
mode and disables normal detect mode. This feature is
most useful when operating the MAX9851/MAX9853 in
low-power shutdown mode. EXTMICBIASL is monitored
and a hardware interrupt is triggered when a load is
detected. Exit sleep mode to clear the hardware interrupt.
Sleep mode is automatically entered when AVDD is
removed and the battery voltage (PVDD) is still present.
See the Headset Detect section.
Headset Detect Configuration (HSTEST)
00 = Headphone sense bias disconnected.
01 = Headphone sense test 1 (standard headphone
detection).
10 = Headphone sense test 2 (balanced mono head-
phone detection).
11 = Reserved.
Set HRMODE = 000 prior to headset detection to dis-
able the headphone amplifiers.
Shutdown (S
SH
HD
DN
N)
1 = MAX9851/MAX9853 operational.
0 = Complete shutdown.
SDALL is an active-low shutdown bit that overrides all
settings and places the entire MAX9851/MAX9853 in
low-power shutdown.
Clock Input Enable (HFEN)
1 = Enable.
0 = Disable.
HFEN = 1 enables the MCLK input and allows all clock
dependent circuitry to operate.
Analog Low-Frequency Oscillator Enable (LFEN)
1 = Enable.
0 = Disable.
LFEN = 1 enables the analog internal low-frequency
oscillator that is used by the charge pump when MCLK
is disabled.
Charge-Pump Enable (CPEN)
1 = Enable.
0 = Disable.
Always program to 1 for proper operation.
Charge-Pump Oscillator Select (CPCLK)
1 = Charge-pump oscillator derived from MCLK.
0 = Charge-pump oscillator derived from internal oscillator.
CPCLK = 1 configures the charge pump to use MCLK
as a clock source. CPCLK = 0 configures the internal
oscillator to be used instead of the MCLK.
CPCLK
must bet set to 1 when the Class D amplifier is
being used (MAX9851 only).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9851EVKIT | 功能描述:音頻 IC 開發(fā)工具 Evaluation Kit/Evaluation System for the MAX9851 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| MAX9853ETM+ | 功能描述:接口—CODEC Stereo Audio CODEC w/DirectDrive Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| MAX9853ETM+T | 功能描述:接口—CODEC Stereo Audio CODEC w/DirectDrive Amp RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| MAX9853EVCMODU | 功能描述:音頻 IC 開發(fā)工具 Evaluation Kit/Evaluation System for the MAX9853 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| MAX9853EVKIT | 功能描述:音頻 IC 開發(fā)工具 Evaluation Kit/Evaluation System for the MAX9853 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
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