參數(shù)資料
型號: MAX98089EWY+T
廠商: Maxim Integrated Products
文件頁數(shù): 96/131頁
文件大小: 0K
描述: IC CODEC AUDIO FLEXSOUND 63WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
系列: FlexSound™
類型: 立體聲音頻
數(shù)據(jù)接口: I²C,串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
動態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 93 / 101
電壓 - 電源,模擬: 1.65 V ~ 2 V
電壓 - 電源,數(shù)字: 1.65 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 63-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 63-WLP
包裝: 帶卷 (TR)
Low-Power, Stereo Audio Codec
with FlexSound Technology
Power Management
The IC includes comprehensive power management to allow the disabling of all unused circuits, minimizing supply
current.
Table 2. Power Management Registers
REGISTER
BIT
NAME
DESCRIPTION
0x51
7
SHDN
Global Shutdown. Disables everything except the headset detection circuitry, which is
controlled separately.
0 = Device Shutdown
1 = Device Enabled
6
VBATEN
See the Battery Measurement section.
3
PERFMODE
Performance Mode. Selects DAC to headphone playback performance mode.
0 = High performance playback mode.
1 = Low power playback mode.
2
HPPLYBCK
Headphone Only Playback Mode. Configures System Bias Control register bits for low
power playback when using DAC to headphone playback path only. When enabled, this
bit overrides the System Bias Control register settings. When disabled, the System Bias
Control register is used to enable system bias blocks. Set both HPPLYBCK and PER-
FMODE for lowest power consumption when using DAC to headphone playback path
only.
0 = Disabled
1 = Enabled
1
PWRSV8K
8kHz Power Save Mode. PWRSV8K configures the ADC for reduced power consump-
tion when fS = 8kHz. PWRSV8K can be used in conjunction with PWRSV when fS = 8kHz
for more power savings.
0 = Normal, high-performance mode.
1 = Low power mode.
0
PWRSV
Power Save Mode. PWRSV configures the ADC for reduced power consumption for all
sample rates. PWRSV can be used in conjunction with PWRSV8K for more power sav-
ings.
0 = Normal, high-performance mode.
1 = Low-power mode.
0x4C
7
INAEN
Line Input A Enable
0 = Disabled
1 = Enabled
6
INBEN
Line Input B Enable
0 = Disabled
1 = Enabled
3
MBEN
Microphone Bias Enable
0 = Disabled
1 = Enabled
1
ADLEN
Left ADC Enable
0 = Disabled
1 = Enabled
0
ADREN
Right ADC Enable
0 = Disabled
1 = Enabled
Maxim Integrated
67
MAX98089
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