參數(shù)資料
型號: MAX9729ETI+T
廠商: Maxim Integrated Products
文件頁數(shù): 28/28頁
文件大?。?/td> 0K
描述: IC AMP AUDIO .052W STER 28TQFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
系列: DirectDrive®
類型: AB 類
輸出類型: 耳機,2-通道(立體聲)
在某負載時最大輸出功率 x 通道數(shù)量: 52mW x 2 @ 32 歐姆
電源電壓: 1.8 V ~ 3.6 V
特點: 帶低音增強模式,消除爆音,I²C,輸入多路復用器,短路和熱保護,關(guān)機,音量控制
安裝類型: 表面貼裝
供應商設(shè)備封裝: 28-TQFN-EP(5x5)
封裝/外殼: 28-WFQFN 裸露焊盤
包裝: 帶卷 (TR)
MAX9729
Stereo Headphone Amplifier with BassMax,
Volume Control, and Input Mux
_______________________________________________________________________________________
9
MAX9729 toc28
20ms/div
200mV/div
100mV/div
FADER OPERATION
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX9729
toc29
SUPPLY VOLTAGE (V)
SUPPLY
CURRENT
(mA)
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3
4
5
6
2
1.8
3.6
NO LOAD
INPUTS AC-GROUNDED
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
MAX9729
toc30
SUPPLY VOLTAGE (V)
SUPPLY
CURRENT
A)
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
7
0
2
1
3
4
5
6
1.8
3.6
Typical Operating Characteristics (continued)
(VDD = PVDD = SHDN = 3V, PGND = SGND = 0V, C1 = C2 = C3 = 1F, CIN = 1F (1206 case size, X7R dielectric ceramic capacitor),
BM_ = 0V, maximum gain setting = 3.5dB, volume attenuation setting = 0dB (total voltage gain = 3.5dB), BassMax disabled. Load
connected between OUT_ and PGND where specified. THD+N measurement BW = 22Hz to 22kHz. Both channels loaded and driven
in phase. TA = +25°C, unless otherwise noted.)
Pin Description
PIN
NAME
FUNCTION
1
INR2
Right-Channel Input 2
2
INR3
Right-Channel Input 3
3
SGND
Signal Ground. Connect SGND to PGND at a single point on the PCB near the device.
4, 8, 15,
22
N.C.
No Connection. Not internally connected.
5
ADD
Slave Address Selection Input. Connect ADD to VDD to set the device slave address to 1010001 or to
PGND to set the device slave address to 1010000.
6PVSS
Charge-Pump Output. Connect to SVSS.
7
SDA
Serial Data Input. Connect a pullup resistor greater than 500
Ω from SDA to PVDD.
9
C1N
Charge-Pump Flying Capacitor Negative Terminal. Connect a 1F capacitor between C1P and C1N.
10
PGND
Power Ground. Connect PGND to SGND at a single point on the PCB near the device.
11
C1P
Charge-Pump Flying Capacitor Positive Terminal. Connect a 1F capacitor between C1P and C1N.
12
SCL
Serial Clock Input. Connect a pullup resistor greater than 500
Ω from SCL to PVDD.
13
PVDD
Charge-Pump and Logic Power-Supply Input. Bypass PVDD to PGND with a 1F capacitor and connect
to VDD. PVDD and VDD are internally connected and should each have a 1F bypass capacitor located
as close to the device as possible.
14
SVSS
Headphone Amplifier Negative Power-Supply Input. Connect to PVSS and bypass with a 1F capacitor
to PGND.
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