參數(shù)資料
型號: MAX9597CTI+T
廠商: Maxim Integrated Products
文件頁數(shù): 7/32頁
文件大小: 0K
描述: IC AUD/VID INTERACE 28TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 音頻/視頻接口
應(yīng)用: DVD,機(jī)頂盒
安裝類型: 表面貼裝
封裝/外殼: 28-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX9597
Low-Power Audio/Video Interface
for Single SCART Connectors
______________________________________________________________________________________
15
Video Reconstruction Filter
The video DAC outputs of the set-top box decoder chip
need to be lowpass-filtered to reject the out-of-band
noise. The MAX9597 integrates sixth-order, Butterworth
filters. The filter passband (±1dB) is typically 10MHz,
and the attenuation at 27MHz is 43dB. The filters are
suited for standard-definition video.
Video Outputs
The video output amplifiers can both source and sink
load current, allowing output loads to be DC- or
AC-coupled. The amplifier output stage needs approxi-
mately 300mV of headroom from either supply rail.
If the supply voltage is greater than 3.135V (5% below
a 3.3V supply), each amplifier can drive two DC-cou-
pled video loads to ground. If the supply is less than
3.135V, each amplifier can drive only one DC-coupled
or AC-coupled video load.
The SCART standard allows for video signals to have a
superimposed DC component within 0V and 2V.
Therefore, most video signals are DC-coupled at the out-
put. In the unlikely event that the video signal needs to
be AC-coupled, the coupling capacitors should be
220F or greater to keep the highpass filter formed by
the 37.5 equivalent resistance of the video transmis-
sion line to a corner frequency of 4.8Hz or below to keep
it well below the 25Hz frame rate of the PAL standard.
The video outputs can be enabled or disabled by bits 1
to 5 of register 0Dh. See Table 11.
Slow Switching
The MAX9597 supports the IEC 933-1, Amendment 1,
trilevel slow-switching standard that selects the aspect
ratio for the display (TV). Under I2C control, the
MAX9597 sets the slow-switching output voltage level.
Table 2 shows the valid input levels of the slow-switch-
ing signal and the corresponding operating modes of
the display device.
One port is available for slow-switching signals for the
TV. The slow-switching outputs can be set to a logic
level or high impedance by writing to bit 0 and 1 of reg-
ister 07h. See Table 9.
VIDEO ORIGIN
FORMAT
VOLTAGE RANGE
(V)
COUPLING
INPUT CIRCUIT CONFIGURATION
External
CVBS
Unknown
AC
Transparent sync-tip clamp
External
RGB
Unknown
AC
Transparent sync-tip clamp
External
Y
Unknown
AC
Transparent sync-tip clamp
External
C
Unknown
AC
Bias circuit
Internal
CVBS
0 to 1
DC
Transparent sync-tip clamp
Internal
R, G, B
0 to 1
DC
Transparent sync-tip clamp
Internal
Y, C
0 to 1
DC
Transparent sync-tip clamp
Internal
Y, Pb, Pr
0 to 1
DC
Transparent sync-tip clamp
Internal
CVBS
2.3 to 3.3
AC
Transparent sync-tip clamp
Internal
R, G, B
2.3 to 3.3
AC
Transparent sync-tip clamp
Internal
Y
2.3 to 3.3
AC
Transparent sync-tip clamp
Internal
C
2.3 to 3.3
AC
Bias circuit
Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit
Configuration**
**
Use a 0.1F capacitor to AC-couple a video signal into the MAX9597.
SLOW-SWITCHING
SIGNAL VOLTAGE
(V)
MODE
0 to 2
Display device uses an internal
source such as a built-in tuner to
provide a video signal.
4.5 to 7.0
Display device uses a video signal
from the SCART connector and sets
the display to a 16:9 aspect ratio.
9.5 to 12.6
Display device uses a signal from the
SCART connector and sets the
display to a 4:3 aspect ratio.
Table 2. Slow-Switching Modes
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