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參數(shù)資料
| 型號： | MAX9485EUP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PROG 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘發(fā)生器 |
| PLL： | 是 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:3 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 73.728MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
The internal power-on reset completes after 1024
cycles of the reference clock starting when VDD is
greater than 2.2V with a tolerance of ±0.4V. When
using the internal power-on reset, RST must be high.
Figure 3 shows power-on reset timing. The internal
reset function also accepts an external forced reset by
driving RST = low. The reset is triggered when RST =
low and completes after 1024 reference clock cycles.
When a reset is initiated, any pulses on RST during the
1024 reference clock cycles are ignored. If RST is held
low at the end of a reset cycle, reset does not initiate
until a high-to-low transition is detected at RST. Figure
4 shows external reset timing.
Software and Hardwire Control Modes
The MAX9485 sampling frequency, sampling rate, and
clock outputs can be programmed through the I2C
2-wire interface (software mode, MODE = low), or
hardwired directly through three-level inputs (hardwire
mode, MODE = high). The offered functions for each
mode are shown in Table 2. CLK_OUT and MCLK are
pulled low when disabled.
Hardwire Mode Programming
(MODE = High)
In hardwire mode, FS2 selects the sampling rate (Table
3). With FS2 = low, the sampling rate is standard. With
FS2 = high, the sampling rate is doubled. When FS2 =
open, the 12kHz standard rate is selected, overriding
the setting of FS0. FS1 selects the scaling factors: 256,
384, and 768 (Table 4). FS0 selects the sample
frequencies: 32kHz, 44.1kHz, and 48kHz (Table 5).
When MODE = high, inputs SAO1 and SAO2 enable or
disable the clock outputs (Tables 6 and 7). CLK_OUT
and MCLK are pulled low when disabled.
MAX9485
Programmable Audio Clock Generator
_______________________________________________________________________________________
9
1.8V
2.6V
POWER-ON RESET RANGE
RESET
REMOVAL
RESET PERIOD =
1024 CYCLES AT 27MHz
INTERNAL
RESET
VDD
2.2V
FUNCTIONS
HARDWIRE
MODE
MODE = HIGH
SOFTWARE
MODE
MODE = LOW
Standard sampling
frequencies:
12kHz, 32kHz,
44.1kHz, 48kHz
Double sampling
frequencies:
64kHz, 88.2kHz, 96kHz
CLK_OUT1, CLK_OUT2,
MCLK:
enable/disable
Figure 3. Power-On Reset Timing
RESET
REMOVAL
(MIN: 20ns)
RESET PERIOD =
1024 CYCLES AT 27MHz
INTERNAL
RESET
RST
Figure 4. External Reset Timing
Table 2. Selectable Functions
FS2
SAMPLING RATE
Low
Standard (32kHz, 44.1kHz, 48kHz)
High
Doubled (64kHz, 88.2kHz, 96kHz)
Open
Standard (12kHz)
Table 3. Sampling Rate Selection
FS1
OUTPUT SCALING FACTOR
Low
256
High
384
Open
768
Table 4. Frequency Scaling Factors
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9485EVKIT | 制造商:Maxim Integrated Products 功能描述:PROGRAMMABLE AUDIO CLOCK GENERATOR - Bulk |
| MAX9486EUG | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 35.328MHz Clock Synthesizer RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX9486EUG-T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 35.328MHz Clock Synthesizer RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MAX9486EVKIT | 制造商:Maxim Integrated Products 功能描述:8KHZ REFERENCE CLOCK SYNTHESIZER WI - Bulk |
| MAX9489ETJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
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