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參數(shù)資料
| 型號： | MAX9374AESA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Differential LVPECL-to-LVDS Translators |
| 中文描述： | PECL TO LVDS TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 167K |
| 代理商： | MAX9374AESA |
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Detailed Description
The MAX9374/MAX9374A are 2.0GHz differential
LVPECL-to-LVDS translators. The output is differential
LVDS and conforms to the ANSI TIA/EIA-644 LVDS
standard. The inputs are biased with internal resistors
such that the output is differential low when inputs are
open. An on-chip V
BB
reference output is available for
single-ended input operation. The MAX9374 is
designed for low-voltage operation from 2.375V to
2.625V in systems with a nominal 2.5V supply. The
MAX9374A is designed for 3.0V to 3.6V operation in
systems with a nominal 3.3V supply.
Differential LVPECL Input
The MAX9374/MAX9374A accept differential LVPECL
inputs and can be configured to accept single-ended
inputs through the use of the V
BB
voltage reference out-
put. The maximum magnitude of the differential signal
applied to the input is 3.0V or V
CC
, whichever is less.
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
Specifications for the high and low voltages of a differ-
ential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously.
Single-Ended Inputs and V
BB
The differential inputs can be configured to accept a
single-ended input through the use of the V
BB
refer-
ence voltage. A noninverting, single-ended input is pro-
duced by connecting V
BB
to the
D
input and applying a
single-ended input signal to the D input. Similarly, an
inverting input is produced by connecting V
BB
to the D
input and applying the input signal to the
D
input. With
a differential input configured as single ended (using
V
BB
), the single-ended input can be driven to V
CC
and
GND or with a single-ended LVPECL signal. Note that a
single-ended input must be at least V
BB
±95mV or a
differential input of at least 95mV to switch the outputs
to the V
OH
and V
OL
levels specified in the
DC Electrical
Characteristics
table.
When using the V
BB
reference output, bypass it with a
0.01μF ceramic capacitor to V
CC
. If the V
BB
reference is
not used, leave it unconnected. Use V
BB
only for inputs
that are on the same device as the V
BB
reference.
Input Bias Resistors
Internal biasing resistors ensure a (differential) output-
low condition in the event that the inputs are not connect-
ed. The inverting input (
D
) is biased with a 36.5k
pull-
down to V
CC
and a 75k
pullup to GND. The
noninverting input (D) is biased with a 75k
pullup to
V
CC
and 75k
pulldown to GND.
Differential LVDS Output
The differential outputs conform to the ANSI TIA/EIA-644
LVDS standard. Typically, terminate the outputs with 100
across Q and
Q
, as shown in the
Typical Application
Circuit
. The outputs are short-circuit protected.
Applications Information
Supply Bypassing
Bypass V
CC
to GND with high-frequency surface-mount
ceramic 0.1μF and 0.01μF capacitors in parallel and as
close to the device as possible, with the 0.01μF capaci-
tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the V
BB
ref-
erence output, bypass it with a 0.01μF ceramic capaci-
tor to V
CC
(if the V
BB
reference is not used, it can be
left open).
Controlled-Impedance Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9374/MAX9374A. Connect high-fre-
quency input and output signals to 50
characteristic
impedance traces. Minimize the number of vias to pre-
vent impedance discontinuities. Reduce reflections by
maintaining the 50
characteristic impedance through
cables and connectors. Reduce skew within a differen-
tial pair by matching the electrical length of the traces.
Output Termination
Terminate the outputs with 100
across Q and
Q
as
shown in the
Typical Application Circuit
. Both outputs
must be terminated.
Differential LVPECL-to-LVDS Translators
6
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX9374EKA-T | Differential LVPECL-to-LVDS Translators |
| MAX9374ESA | Differential LVPECL-to-LVDS Translators |
| MAX9374 | Differential LVPECL-to-LVDS Translators |
| MAX9374A | Differential LVPECL-to-LVDS Translators |
| MB15F8XUL | Fractional-N / Integer dual PLL Frequency Synthesizers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9374AESAT | 制造商:Maxim Integrated Products 功能描述: |
| MAX9374EKA | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL LVPECL-TO-LVDS TRANSLA - Rail/Tube |
| MAX9374EKA-T | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL LVPECL-TO-LVDS TRANSLATORS - Tape and Reel 制造商:Rochester Electronics LLC 功能描述: |
| MAX9374ESA | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL LVPECL-TO-LVDS TRANSLATORS - Rail/Tube 制造商:Rochester Electronics LLC 功能描述: |
| MAX9375EUA | 功能描述:轉(zhuǎn)換 - 電壓電平 Single LVDS/Anything To-LVPECL Translator RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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