參數(shù)資料
型號: MAX9374AESA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 通用總線功能
英文描述: Differential LVPECL-to-LVDS Translators
中文描述: PECL TO LVDS TRANSLATOR, COMPLEMENTARY OUTPUT, PDSO8
封裝: MS-012AA, SOIC-8
文件頁數(shù): 3/9頁
文件大?。?/td> 167K
代理商: MAX9374AESA
M
Differential LVPECL-to-LVDS Translators
_______________________________________________________________________________________
3
DC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 2.375V to 2.625V for MAX9374, V
CC
= 3.0V to 3.6V for MAX9374A, 100
±1% across outputs, V
ID
= 0.095V to V
CC
or 3V,
whichever is less, V
IHD
= 1.2V to V
CC
, V
ILD
= GND to V
CC
- 0.095V, unless otherwise noted. Typical values are at V
IHD
= 2.0V, V
ILD
=
1.85V, V
CC
= 3.3V for MAX9374A, V
CC
= 2.5V for MAX9374.) (Notes 1, 2)
-40
°
C
TYP
+25
°
C
TYP
+85
°
C
TYP
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
Change in V
OD
Between
Complementary Output
States
Output Offset Voltage
Change in V
OS
Between
Complementary Output
States
Output Short-Circuit
Current
V
BB
AND SUPPLY
V
OD
1
25
1
25
1
25
mV
V
OS
1.125
1.25
1.375 1.125
1.25
1.375 1.125
1.25
1.375
V
V
OS
3
25
3
25
3
25
mV
I
OSC
Q or
Q
short to
GND
23
30
23
30
23
30
mA
Reference Voltage
V
BB
I
BB
= ±0.6mA
(Note 4)
(Note 5)
V
CC
-
1.38
V
CC
-
1.26
30
V
CC
-
1.38
V
CC
-
1.26
30
V
CC
-
1.38
V
CC
-
1.26
30
V
Supply Current
I
CC
16
18
20
mA
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.375V to 2.625V for MAX9374, V
CC
= 3.0V to 3.6V for MAX9374A, 100
±1% across outputs, V
IHD
- V
ILD
= 0.15V to V
CC
or
3V, whichever is less, V
IHD
= 1.2V to V
CC
, V
ILD
= GND to V
CC
- 0.15V, f
IN
= 1GHz, input transition time = 125ps, input duty cycle =
50%, unless otherwise noted. Typical values are at V
IHD
= 2.0V, V
ILD
= 1.85V, V
CC
= 3.3V for MAX9374A, V
CC
= 2.5V for MAX9374,
unless otherwise noted.) (Notes 1, 6)
-40
°
C
TYP
+25
°
C
TYP
+85
°
C
TYP
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
Differential Input to
Differential Output Delay
Single-Ended Input to
Differential Output Delay
Part-to-Part Skew
t
PLHD
,
t
PHLD
t
PLHS
,
t
PHLS
t
SKPP
Figure 1
116
240
420
128
250
403
145
260
440
ps
Figure 1
126
250
430
138
250
415
155
260
450
ps
(Note 7)
f
IN
= 1.0GHz,
clock pattern
f
IN
= 2.0GHz,
clock pattern
f
IN
= 2.0Gbps,
2
23
-1 PRBS
pattern
V
OD
250mV
20% to 80%,
Figure 1
304
275
295
ps
0.9
2
1
2
1
2
Added Random Jitter
(Note 8)
t
RJ
0.8
2
0.9
2
0.9
2
ps
(RMS)
Added Deterministic
Jitter (Note 8)
t
DJ
45
75
46
75
38
75
ps
(P-P)
Operating Frequency
f
MAX
2.0
2.2
2.0
2.2
2.0
2.2
MHz
Output Rise/Fall Time
t
R
, t
F
92
200
91
200
90
200
ps
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