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參數(shù)資料
| 型號(hào)： | MAX9374AEKA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 0K |
| 描述： | IC TRANSLATOR DIFF SOT23-8 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 邏輯功能： | 變換器 |
| 位數(shù)： | 1 |
| 輸入類型： | LVPECL |
| 輸出類型： | LVDS |
| 通道數(shù)： | 1 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 是/是 |
| 傳輸延遲（最大）： | 0.091ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
MAX9374/MAX9374A
Detailed Description
The MAX9374/MAX9374A are 2.0GHz differential
LVPECL-to-LVDS translators. The output is differential
LVDS and conforms to the ANSI TIA/EIA-644 LVDS
standard. The inputs are biased with internal resistors
such that the output is differential low when inputs are
open. An on-chip VBB reference output is available for
single-ended input operation. The MAX9374 is
designed for low-voltage operation from 2.375V to
2.625V in systems with a nominal 2.5V supply. The
MAX9374A is designed for 3.0V to 3.6V operation in
systems with a nominal 3.3V supply.
Differential LVPECL Input
The MAX9374/MAX9374A accept differential LVPECL
inputs and can be configured to accept single-ended
inputs through the use of the VBB voltage reference out-
put. The maximum magnitude of the differential signal
applied to the input is 3.0V or VCC, whichever is less.
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
Specifications for the high and low voltages of a differ-
ential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously.
Single-Ended Inputs and VBB
The differential inputs can be configured to accept a
single-ended input through the use of the VBB refer-
ence voltage. A noninverting, single-ended input is pro-
duced by connecting VBB to the D input and applying a
single-ended input signal to the D input. Similarly, an
inverting input is produced by connecting VBB to the D
input and applying the input signal to the D input. With
a differential input configured as single ended (using
VBB), the single-ended input can be driven to VCC and
GND or with a single-ended LVPECL signal. Note that a
single-ended input must be at least VBB ±95mV or a
differential input of at least 95mV to switch the outputs
to the VOH and VOL levels specified in the DC Electrical
Characteristics table.
When using the VBB reference output, bypass it with a
0.01F ceramic capacitor to VCC. If the VBB reference is
not used, leave it unconnected. Use VBB only for inputs
that are on the same device as the VBB reference.
Input Bias Resistors
Internal biasing resistors ensure a (differential) output-
low condition in the event that the inputs are not connect-
ed. The inverting input (D) is biased with a 36.5k
pull-
down to VCC and a 75k
pullup to GND. The
noninverting input (D) is biased with a 75k
pullup to
VCC and 75k
pulldown to GND.
Differential LVDS Output
The differential outputs conform to the ANSI TIA/EIA-644
LVDS standard. Typically, terminate the outputs with 100
across Q and Q, as shown in the Typical Application
Circuit. The outputs are short-circuit protected.
Applications Information
Supply Bypassing
Bypass VCC to GND with high-frequency surface-mount
ceramic 0.1F and 0.01F capacitors in parallel and as
close to the device as possible, with the 0.01F capaci-
tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the VBB ref-
erence output, bypass it with a 0.01F ceramic capaci-
tor to VCC (if the VBB reference is not used, it can be
left open).
Controlled-Impedance Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9374/MAX9374A. Connect high-fre-
quency input and output signals to 50
characteristic
impedance traces. Minimize the number of vias to pre-
vent impedance discontinuities. Reduce reflections by
maintaining the 50
characteristic impedance through
cables and connectors. Reduce skew within a differen-
tial pair by matching the electrical length of the traces.
Output Termination
Terminate the outputs with 100
across Q and Q as
shown in the Typical Application Circuit. Both outputs
must be terminated.
Differential LVPECL-to-LVDS Translators
6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9374AESA | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL LVPECL-TO-LVDS TRANSLATORS - Rail/Tube 制造商:Rochester Electronics LLC 功能描述: |
| MAX9374AESAT | 制造商:Maxim Integrated Products 功能描述: |
| MAX9374EKA | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL LVPECL-TO-LVDS TRANSLA - Rail/Tube |
| MAX9374EKA-T | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL LVPECL-TO-LVDS TRANSLATORS - Tape and Reel 制造商:Rochester Electronics LLC 功能描述: |
| MAX9374ESA | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL LVPECL-TO-LVDS TRANSLATORS - Rail/Tube 制造商:Rochester Electronics LLC 功能描述: |
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