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參數(shù)資料
| 型號： | MAX9321EKA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 8/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA DRVR 1:1 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/數(shù)據(jù)驅(qū)動(dòng)器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVECL，LVPECL |
| 輸出： | LVECL，LVPECL |
| 頻率 - 最大： | 3GHz |
| 電源電壓： | 2.25 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
MAX9321/MAX9321A
Differential LVPECL/LVECL/HSTL
Receiver/Drivers
8
_______________________________________________________________________________________
When using the VBB reference output, bypass it with a
0.01F ceramic capacitor to VCC. If the VBB reference
is not used, it can be left open. The VBB reference can
source or sink 0.5mA. Use VBB only for an input on the
same device as the VBB reference.
The maximum magnitude of the differential input from D
to D is 3.0V or VCC - VEE, whichever is less. This limit
also applies to the difference between any reference
voltage input and a single-ended input.
The differential input has bias resistors that drive the
output to a differential low when the inputs are open.
The inverting input is biased with a 60k
pullup to VCC
and a 100k
pulldown to VEE. The noninverting input is
biased with a 100k
pulldown to VEE.
Specifications for the high and low voltage of the differ-
ential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously (VILD cannot
be higher than VIHD).
Outputs
Output levels are referenced to VCC and are consid-
ered LVPECL or LVECL, depending on the level of the
VCC supply. With VCC connected to a positive supply
and VEE connected to GND, the output is LVPECL. The
output is LVECL when VCC is connected to GND and
VEE is connected to a negative supply.
A single-ended input of at least VBB ±100mV or a differ-
ential input of at least ±100mV switches the outputs to
the VOH and VOL levels specified in the DC Electrical
Characteristics table.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1F and 0.01F capacitors in parallel as
close to the device as possible, with the 0.01F value
capacitor closest to the device. Use multiple parallel
vias for low inductance. When using the VBB reference
output, bypass it with a 0.01F ceramic capacitor to
VCC (if the VBB reference is not used, it can be left
open).
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9321/MAX9321A. Connect each sig-
nal of a differential input or output to a 50
characteristic impedance trace. Minimize the number of
vias to prevent impedance discontinuities. Reduce
reflections by maintaining the 50
characteristic
impedance through connectors and across cables.
Reduce skew within a differential pair by matching the
electrical length of the traces.
The exposed-pad (EP) SO package can be soldered to
the PC board for enhanced thermal performance. If the
EP is not soldered to the PC board, the thermal resis-
tance is the same as the regular SO package. The EP is
connected to the chip VEE supply. Be sure that the pad
does not touch signal lines or other supplies.
Contact Maxim's Packaging department for guidelines
on the use of EP packages.
Output Termination
Terminate outputs through 50
to VCC - 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from the differential output, terminate
both outputs. For example, when Q is used as a single-
ended output, terminate both Q and Q.
Chip Information
TRANSISTOR COUNT: 162
6
SOT23
D
VCC 1
2
3
4
8
5
7
VEE
MAX9321A
60k
100k
100k
VCC
VEE
6
MAX/SO
1
2
3
4
8
5
7
MAX9321A
D
N.C.
VBB
Q
60k
100k
100k
VCC
Q
VEE
VCC
N.C.
VBB
D
Q
D
Pin Configurations (continued)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9321ESA | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL LVPECL/LVECL/HSTL RECEIVER/DRIVE - Rail/Tube 制造商:Rochester Electronics LLC 功能描述: |
| MAX9321EUA | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL LVPECL/LVECL/HSTL RECEIVER/DRIVE - Rail/Tube |
| MAX9321EUA+ | 功能描述:總線收發(fā)器 LVPECL/LVECL/HSTL Receiver/Driver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MAX9321EUA+T | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 LVPECL/LVECL/HSTL Receiver/Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MAX9322ECY+ | 制造商:Maxim Integrated Products 功能描述:DIFFERENTIAL DIVIDE-BY-1/DIVIDE-BY-2 CLOCK DRVR 52TQFP - Rail/Tube |
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