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參數(shù)資料
| 型號： | MAX9316EWP-T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:5 20-SOIC |
| 標準包裝： | 1,000 |
| 類型： | 扇出緩沖器（分配），多路復用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HSTL，LVECL，LVPECL |
| 輸出： | LVECL，LVPECL |
| 頻率 - 最大： | 1.5GHz |
| 電源電壓： | 3 V ~ 3.8 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
ed), allowing high-performance clock or data distribu-
tion in systems with a nominal +3.3V supply. For inter-
facing to differential LVECL, the VEE range is -3.0V to
-3.8V (with VCC grounded). Output levels are refer-
enced to VCC and are considered LVPECL or LVECL,
depending on the level of the VCC supply. With VCC
connected to a positive supply and VEE connected to
ground, the outputs are LVPECL. The outputs are
LVECL when VCC is connected to ground and VEE is
connected to a negative supply.
Input Bias Resistors
When the inputs are open, the internal bias resistors set
the inputs to low state. The inverting input (CLK) is
biased with a 75k
pullup to VCC and a 75k pulldown
to VEE. The noninverting inputs (CLK) and the single-
ended input (SCLK) are each biased with a 75k
pull-
down to VEE. The single-ended EN and SEL inputs are
each biased with a 60k
pulldown to VEE.
Differential Clock Input Limits
The maximum magnitude of the differential signal applied
to the differential clock input is 3.0V. This limit also
applies to the difference between any reference voltage
input and a single-ended input. Specifications for the high
and low voltages of a differential input (VIHD and VILD)
and the differential input voltage (VIHD - VILD) apply
simultaneously.
Single-Ended Clock Input and VBB
The differential clock input can be configured to accept
a single-ended input. This is accomplished by connect-
ing the on-chip reference voltage, VBB, to the inverting
or noninverting input of the differential input as a refer-
ence. For example, the differential CLK, CLK input is
converted to a noninverting, single-ended input by con-
necting VBB to CLK and connecting the single-ended
input signal to CLK. Similarly, an inverting configuration
is obtained by connecting VBB to CLK and connecting
the single-ended input to CLK. With a differential input
configured as single ended (using VBB), the single-
ended input can be driven to VCC and VEE or with a
single-ended LVPECL/LVECL signal. Note that the sin-
gle-ended input must be least VBB ±95mV or a differ-
ential input of at least 95mV to switch the outputs to the
VOH and VOL levels specified in the DC Electrical
Characteristics table.
When using the VBB reference output, bypass it with a
0.01F ceramic capacitor to VCC. If the VBB reference
is not used, leave it open. The VBB reference can
source or sink 0.5mA. Use VBB only for an input that is
on the same device as the VBB reference.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1F and 0.01F capacitors in parallel as
close to the device as possible, with the 0.01F capaci-
tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the VBB ref-
erence output, bypass it with a 0.01F ceramic capaci-
tor to VCC (if the VBB reference is not used, it can be
left open).
Controlled-Impedance Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9316. Connect input and output sig-
nals with 50
characteristic impedance traces.
Minimize the number of vias to prevent impedance dis-
continuities. Reduce reflections by maintaining the 50
characteristic impedance through cables and connec-
tors. Reduce skew within a differential pair by matching
the electrical length of the traces.
Output Termination
Terminate outputs with 50
to VCC - 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 616
PROCESS: Bipolar
MAX9316
1:5 Differential LVPECL/LVECL/HSTL
Clock and Data Driver
_______________________________________________________________________________________
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| MAX9317AECJ | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MAX9317AECJ+ | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MAX9317AECJ+T | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MAX9317AETJ | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MAX9317AETJ+ | 功能描述:時鐘緩沖器 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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