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參數(shù)資料
| 型號： | MAX9273GTL/V+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/49頁 |
| 文件大小： | 0K |
| 描述： | IC SERIALIZER 22BIT GMSL 40TQFN |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | * |
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MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
18
Maxim Integrated
Figure 12. Power-Up Delay
Detailed Description
The MAX9273 serializer, when paired with the MAX9272
deserializer, provides the full set of operating features,
but offers basic functionality when paired with any GMSL
deserializer.
The serializer has a maximum serial-bit rate of 1.5Gbps
for 15m or more of cable and operates up to a maximum
input clock of 50MHz in 22-bit, single-input mode, or
75MHz/100MHz in 15-bit/11-bit, double-input mode,
respectively. Pre/deemphasis, along with the GMSL
deserializer channel equalizer, extends the link length
and enhances link reliability.
The control channel enables a FC to program serial-
izer and deserializer registers and program registers
on peripherals. The FC can be located at either end of
the link, or at both ends. Two modes of control-channel
operation are available with associated protocols and
data formats. Base mode uses either I2C or GMSL UART,
while bypass mode uses a user-defined UART.
Spread spectrum is available to reduce EMI on the serial
output. The serial output complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
Register Mapping
Registers set the operating conditions of the serializer
and are programmed using the control channel in base
mode. The serializer holds its device address and the
device address of the deserializer it is driving. Similarly,
the driven deserializer holds its device address and the
address of the serializer by which it is driven. Whenever
a device address is changed, be sure to write the new
address to both devices. The default device address of
the MAX9273 serializer (or any GMSL serializer) is 0x80
and the default device address of any GMSL deserial-
izer is 0x90 (Table 1). Registers 0x00 and 0x01 in both
devices hold the device addresses.
Input Bit Map
The parallel input functioning and width depends on
settings of the double-/single-input mode (DBL), HS/VS
encoding (HVEN), error correction (EDC), and bus width
(BWS). DINA are the inputs latched by the pixel clock in
single-input mode, or the inputs latched on the first pixel
clock in double-input mode. DINB are the inputs latched
on the second pixel clock in double-input mode. Table 2
lists the bit map for the control pin settings.
PWDN
POWERED DOWN
VIH1
tPU
REVERSE CONTROL
CHANNEL DISABLED
350s
PCLKIN
POWERED UP,
SERIAL LINK INACTIVE
POWERED UP, SERIAL LINK ACTIVE
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL DISABLED
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