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參數(shù)資料
| 型號(hào)： | MAX9171EKA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RECEIVER LVDS LINE SOT23-8 |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 接收器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 0/1 |
| 規(guī)程： | LVDS |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
In-Path vs. Parallel Fail-Safe
The MAX9171/MAX9172 have in-path fail-safe that is
compatible with in-path fail-safe receivers, such as the
DS90LV018A and DS90LV028A. Refer to the MAX9111/
MAX9113 data sheet for pin-compatible receivers with
parallel fail-safe and lower jitter. Refer to the MAX9130
data sheet for a single LVDS receiver with parallel fail-
safe in an SC70 package.
The MAX9171/MAX9172 with in-path fail-safe are
designed with a +40mV input offset voltage, a 2.5A
current source between VCC and the noninverting
input, and a 5A current sink between the inverting
input and ground (Figure 1). If the differential input is
open, the 2.5A current source pulls the input to VCC -
0.7V and the 5A source sink pulls the inverting input to
ground, which drives the receiver output high. If the dif-
ferential input is shorted or terminated with a typical
value termination resistor, the +40mV offset drives the
receiver output high. If the input is terminated and float-
ing, the receiver output is driven high by the +40mV off-
set, and the 2:1 current sink to current source ratio
(5A:2.5A) pulls the inputs to ground. This can be an
advantage when switching between drivers on a multi-
point bus because the change in common-mode volt-
age from ground to the typical driver offset voltage of
1.2V is not as much as the change from VCC to 1.2V
(parallel fail-safe pulls the bus to VCC). Figure 2 shows
the propagation delay and transition test time circuit
and Figure 3 shows the propagation delay and transi-
tion test time waveforms.
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
_______________________________________________________________________________________
7
OUT_
VCC
IN_+
IN_-
5
A
2.5
A
40mV
Figure 1. Input with In-Path Fail-Safe Network Equivalent Circuit
50
50
IN_-
OUT_
IN_+
15pF
PULSE
GENERATOR
Figure 2. Propagation Delay and Transition Test Time Circuit
IN_+
IN_-
tPLHD
20%
80%
OUT_
VOH
VOL
1.5V
20%
80%
1.2V (0V DIFFERENTIAL)
VID = 0.2V
1.3V
1.1V
tPHLD
tTHL
tTLH
Figure 3. Propagation Delay and Transition Time Waveforms
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9171ESA | 制造商:Maxim Integrated Products 功能描述:SINGLE/DUAL LVDS LINE RECEIVERS WITH IN-PATH" - Bulk |
| MAX9171ESA+ | 制造商:Maxim Integrated Products 功能描述:LINE RCVR 1RX 8SOIC N - Rail/Tube |
| MAX9171ESA+T | 制造商:Maxim Integrated Products 功能描述:LINE RCVR 1RX 8SOIC N - Tape and Reel |
| MAX9171ETA | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual LVDS Line Receivers with “In-Path” Fail-Safe |
| MAX9172 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Single/Dual LVDS Line Receivers with “In-Path” Fail-Safe |
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