CONDITIONS: 3.3V, PRBS = 223
參數(shù)資料
型號(hào)： MAX9152ESE+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 7/12頁(yè)
文件大?。?/td> 0K
描述： IC CROSSPOINT SWITCH 2X2 16SOIC
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 50
功能： 交叉點(diǎn)開(kāi)關(guān)
電路： 1 x 2:2
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 管件
DIFFERENTIAL OUTPUT EYE PATTERN
IN 1:2 SPLITTER MODE AT 800Mbps
CONDITIONS: 3.3V, PRBS = 223 -1 DATA PATTERN,
|VID| = 200mV, VCM = +1.2V
HORIZONTAL SCALE = 200ps/div
VERTICAL SCALE = 100mV/div
MAX9152
toc01
150
250
350
450
550
650
50
100
75
125
150
175
200
DIFFERENTIAL
OUTPUT VOLTAGE vs. LOAD
MAX9152
toc02
LOAD RESISTOR (
)
DIFFERENTIAL
OUTPUT
VOLTAGE
(mV)
NC/RSEL = LOW OR OPEN
NC/RSEL = HIGH
30
32
36
34
38
40
100
300
200
400
500
600
700
800
SUPPLY CURRENT vs. DATA RATE
MAX9152
toc03
DATA RATE (Mbps)
SUPPLY
CURRENT
(mA)
Typical Operating Characteristics
(VCC = +3.3V, RL = 100
, NC/RSEL = high, CL= 5pF, input transition time = 600ps (20% to 80%), VID = 200mV, PRBS = 223 - 1 data
pattern, VCM = +1.2V, TA = +25°C, unless otherwise noted.)
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
4
_______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Pulse Skew |tPLHD -tPHLD| (Note 6)
tSKEW
Figures 5, 6
25
90
ps
Output Channel-to-Channel Skew
tCCS
Figures 5, 7
20
50
ps
Output Low-to-High Transition
Time (20% to 80%)
tLHT
Figures 5, 6
160
270
480
ps
Output High-to-Low Transition
Time (20% to 80%)
tHLT
Figures 5, 6
160
270
480
ps
VID = 200mV, VCM = 1.2V, 50% duty
cycle, 800Mbps, input transition time =
600ps (20% to 80%)
10
30
LVDS Data Path Peak-to-Peak
Jitter (Note 7)
tJIT
VID = 200mV, VCM = 1.2V, PRBS = 2
23 - 1
data pattern, 800Mbps, input transition
time = 600ps (20% to 80%)
65
120
ps
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, NC/RSEL = open for RL = 75
±1%, NC/RSEL = high for RL = 100 ±1%, CL = 5pF, differential input voltage
|VID| = 0.15V to VCC, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage
(VIN+, VIN-) = 0 to VCC, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, TA = -40°C to +85°C. Typical values
at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25
°C, unless otherwise noted.) (Notes 3, 4)
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VID, VOD, and
VOD.
Note 2: Guaranteed by design and characterization, not production tested.
Note 3: AC parameters are guaranteed by design and characterization.
Note 4: CL includes scope probe and test jig capacitance.
Note 5: tSET and tHOLD time specify that data must be in a stable state before and after the SEL transition.
Note 6: tSKEW is the magnitude difference of differential propagation delay over rated conditions; tSKEW = |tPHLD - tPLHD|.
Note 7: Specification includes test equipment jitter.
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